net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it

[linux-2.6-microblaze.git] / drivers / net / ethernet / stmicro / stmmac / dwmac-meson8b.c

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index a3934ca..c9ec0cb 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/device.h>
@@ -32,7 +33,6 @@
 #define PRG_ETH0_CLK_M250_SEL_SHIFT    4
 #define PRG_ETH0_CLK_M250_SEL_MASK     GENMASK(4, 4)
 
-#define PRG_ETH0_TXDLY_SHIFT           5
 #define PRG_ETH0_TXDLY_MASK            GENMASK(6, 5)
 
 /* divider for the result of m250_sel */
@@ -262,7 +262,8 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
                                        PRG_ETH0_INVERTED_RMII_CLK, 0);
 
                meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
-                                       tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
+                                       FIELD_PREP(PRG_ETH0_TXDLY_MASK,
+                                                  tx_dly_val));
 
                /* Configure the 125MHz RGMII TX clock, the IP block changes
                 * the output automatically (= without us having to configure