Merge tag 'mtd/for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

[linux-2.6-microblaze.git] / drivers / mtd / spi-nor / micron-st.c

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 8920547..3c6499f 100644 (file)
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -11,6 +11,7 @@
 /* flash_info mfr_flag. Used to read proprietary FSR register. */
 #define USE_FSR                BIT(0)
 
+#define SPINOR_OP_MT_DIE_ERASE 0xc4    /* Chip (die) erase opcode */
 #define SPINOR_OP_RDFSR                0x70    /* Read flag status register */
 #define SPINOR_OP_CLFSR                0x50    /* Clear flag status register */
 #define SPINOR_OP_MT_DTR_RD    0xfd    /* Fast Read opcode in DTR mode */
@@ -192,6 +193,50 @@ static struct spi_nor_fixups mt25qu512a_fixups = {
        .post_bfpt = mt25qu512a_post_bfpt_fixup,
 };
 
+static int st_nor_four_die_late_init(struct spi_nor *nor)
+{
+       struct spi_nor_flash_parameter *params = nor->params;
+
+       params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+       params->n_dice = 4;
+
+       /*
+        * Unfortunately the die erase opcode does not have a 4-byte opcode
+        * correspondent for these flashes. The SFDP 4BAIT table fails to
+        * consider the die erase too. We're forced to enter in the 4 byte
+        * address mode in order to benefit of the die erase.
+        */
+       return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
+static int st_nor_two_die_late_init(struct spi_nor *nor)
+{
+       struct spi_nor_flash_parameter *params = nor->params;
+
+       params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+       params->n_dice = 2;
+
+       /*
+        * Unfortunately the die erase opcode does not have a 4-byte opcode
+        * correspondent for these flashes. The SFDP 4BAIT table fails to
+        * consider the die erase too. We're forced to enter in the 4 byte
+        * address mode in order to benefit of the die erase.
+        */
+       return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
+static struct spi_nor_fixups n25q00_fixups = {
+       .late_init = st_nor_four_die_late_init,
+};
+
+static struct spi_nor_fixups mt25q01_fixups = {
+       .late_init = st_nor_two_die_late_init,
+};
+
+static struct spi_nor_fixups mt25q02_fixups = {
+       .late_init = st_nor_four_die_late_init,
+};
+
 static const struct flash_info st_nor_parts[] = {
        {
                .name = "m25p05-nonjedec",
@@ -366,16 +411,17 @@ static const struct flash_info st_nor_parts[] = {
                .name = "n25q00",
                .size = SZ_128M,
                .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
-                        SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE,
+                        SPI_NOR_BP3_SR_BIT6,
                .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
                .mfr_flags = USE_FSR,
+               .fixups = &n25q00_fixups,
        }, {
                .id = SNOR_ID(0x20, 0xba, 0x22),
                .name = "mt25ql02g",
                .size = SZ_256M,
-               .flags = NO_CHIP_ERASE,
                .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
                .mfr_flags = USE_FSR,
+               .fixups = &mt25q02_fixups,
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x15),
                .name = "n25q016a",
@@ -429,20 +475,25 @@ static const struct flash_info st_nor_parts[] = {
                         SPI_NOR_BP3_SR_BIT6,
                .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
                .mfr_flags = USE_FSR,
+       }, {
+               .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
+               .name = "mt25qu01g",
+               .mfr_flags = USE_FSR,
+               .fixups = &mt25q01_fixups,
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x21),
                .name = "n25q00a",
                .size = SZ_128M,
-               .flags = NO_CHIP_ERASE,
                .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
                .mfr_flags = USE_FSR,
+               .fixups = &n25q00_fixups,
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x22),
                .name = "mt25qu02g",
                .size = SZ_256M,
-               .flags = NO_CHIP_ERASE,
                .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
                .mfr_flags = USE_FSR,
+               .fixups = &mt25q02_fixups,
        }
 };