Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[linux-2.6-microblaze.git] / drivers / mtd / nand / raw / qcom_nandc.c

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 45de67a..ef0bade 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
 {
        struct nand_chip *chip = &host->chip;
        u32 cmd, cfg0, cfg1, ecc_bch_cfg;
+       struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 
        if (read) {
                if (host->use_ecc)
@@ -762,7 +763,8 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
        nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
        nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
        nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
-       nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
+       if (!nandc->props->qpic_v2)
+               nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
        nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
        nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
        nandc_set_reg(chip, NAND_EXEC_CMD, 1);
@@ -1133,7 +1135,8 @@ static void config_nand_page_read(struct nand_chip *chip)
 
        write_reg_dma(nandc, NAND_ADDR0, 2, 0);
        write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
-       write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+       if (!nandc->props->qpic_v2)
+               write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
        write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
        write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
                      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
@@ -1191,8 +1194,9 @@ static void config_nand_page_write(struct nand_chip *chip)
 
        write_reg_dma(nandc, NAND_ADDR0, 2, 0);
        write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
-       write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
-                     NAND_BAM_NEXT_SGL);
+       if (!nandc->props->qpic_v2)
+               write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
+                             NAND_BAM_NEXT_SGL);
 }
 
 /*
@@ -1248,7 +1252,8 @@ static int nandc_param(struct qcom_nand_host *host)
                                        | 2 << WR_RD_BSY_GAP
                                        | 0 << WIDE_FLASH
                                        | 1 << DEV0_CFG1_ECC_DISABLE);
-       nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
+       if (!nandc->props->qpic_v2)
+               nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
 
        /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
        if (!nandc->props->qpic_v2) {
@@ -2688,7 +2693,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
                                | ecc_mode << ECC_MODE
                                | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
 
-       host->ecc_buf_cfg = 0x203 << NUM_STEPS;
+       if (!nandc->props->qpic_v2)
+               host->ecc_buf_cfg = 0x203 << NUM_STEPS;
 
        host->clrflashstatus = FS_READY_BSY_N;
        host->clrreadstatus = 0xc0;