habanalabs: move driver to accel subsystem

[linux-2.6-microblaze.git] / drivers / misc / habanalabs / include / goya / asic_reg / tpc1_cmdq_regs.h

diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h
deleted file mode 100644 (file)
index 30ae0f3..0000000
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright 2016-2018 HabanaLabs, Ltd.
- * All Rights Reserved.
- *
- */
-
-/************************************
- ** This is an auto-generated file **
- **       DO NOT EDIT BELOW        **
- ************************************/
-
-#ifndef ASIC_REG_TPC1_CMDQ_REGS_H_
-#define ASIC_REG_TPC1_CMDQ_REGS_H_
-
-/*
- *****************************************
- *   TPC1_CMDQ (Prototype: CMDQ)
- *****************************************
- */
-
-#define mmTPC1_CMDQ_GLBL_CFG0                                        0xE49000
-
-#define mmTPC1_CMDQ_GLBL_CFG1                                        0xE49004
-
-#define mmTPC1_CMDQ_GLBL_PROT                                        0xE49008
-
-#define mmTPC1_CMDQ_GLBL_ERR_CFG                                     0xE4900C
-
-#define mmTPC1_CMDQ_GLBL_ERR_ADDR_LO                                 0xE49010
-
-#define mmTPC1_CMDQ_GLBL_ERR_ADDR_HI                                 0xE49014
-
-#define mmTPC1_CMDQ_GLBL_ERR_WDATA                                   0xE49018
-
-#define mmTPC1_CMDQ_GLBL_SECURE_PROPS                                0xE4901C
-
-#define mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS                            0xE49020
-
-#define mmTPC1_CMDQ_GLBL_STS0                                        0xE49024
-
-#define mmTPC1_CMDQ_GLBL_STS1                                        0xE49028
-
-#define mmTPC1_CMDQ_CQ_CFG0                                          0xE490B0
-
-#define mmTPC1_CMDQ_CQ_CFG1                                          0xE490B4
-
-#define mmTPC1_CMDQ_CQ_ARUSER                                        0xE490B8
-
-#define mmTPC1_CMDQ_CQ_PTR_LO                                        0xE490C0
-
-#define mmTPC1_CMDQ_CQ_PTR_HI                                        0xE490C4
-
-#define mmTPC1_CMDQ_CQ_TSIZE                                         0xE490C8
-
-#define mmTPC1_CMDQ_CQ_CTL                                           0xE490CC
-
-#define mmTPC1_CMDQ_CQ_PTR_LO_STS                                    0xE490D4
-
-#define mmTPC1_CMDQ_CQ_PTR_HI_STS                                    0xE490D8
-
-#define mmTPC1_CMDQ_CQ_TSIZE_STS                                     0xE490DC
-
-#define mmTPC1_CMDQ_CQ_CTL_STS                                       0xE490E0
-
-#define mmTPC1_CMDQ_CQ_STS0                                          0xE490E4
-
-#define mmTPC1_CMDQ_CQ_STS1                                          0xE490E8
-
-#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN                                0xE490F0
-
-#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xE490F4
-
-#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT                               0xE490F8
-
-#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xE490FC
-
-#define mmTPC1_CMDQ_CQ_IFIFO_CNT                                     0xE49108
-
-#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xE49120
-
-#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xE49124
-
-#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xE49128
-
-#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xE4912C
-
-#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xE49130
-
-#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xE49134
-
-#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xE49138
-
-#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xE4913C
-
-#define mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xE49140
-
-#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xE49144
-
-#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xE49148
-
-#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xE4914C
-
-#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xE49150
-
-#define mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xE49154
-
-#define mmTPC1_CMDQ_CP_FENCE0_RDATA                                  0xE49158
-
-#define mmTPC1_CMDQ_CP_FENCE1_RDATA                                  0xE4915C
-
-#define mmTPC1_CMDQ_CP_FENCE2_RDATA                                  0xE49160
-
-#define mmTPC1_CMDQ_CP_FENCE3_RDATA                                  0xE49164
-
-#define mmTPC1_CMDQ_CP_FENCE0_CNT                                    0xE49168
-
-#define mmTPC1_CMDQ_CP_FENCE1_CNT                                    0xE4916C
-
-#define mmTPC1_CMDQ_CP_FENCE2_CNT                                    0xE49170
-
-#define mmTPC1_CMDQ_CP_FENCE3_CNT                                    0xE49174
-
-#define mmTPC1_CMDQ_CP_STS                                           0xE49178
-
-#define mmTPC1_CMDQ_CP_CURRENT_INST_LO                               0xE4917C
-
-#define mmTPC1_CMDQ_CP_CURRENT_INST_HI                               0xE49180
-
-#define mmTPC1_CMDQ_CP_BARRIER_CFG                                   0xE49184
-
-#define mmTPC1_CMDQ_CP_DBG_0                                         0xE49188
-
-#define mmTPC1_CMDQ_CQ_BUF_ADDR                                      0xE49308
-
-#define mmTPC1_CMDQ_CQ_BUF_RDATA                                     0xE4930C
-
-#endif /* ASIC_REG_TPC1_CMDQ_REGS_H_ */