+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright 2016-2020 HabanaLabs, Ltd.
- * All Rights Reserved.
- *
- */
-
-/************************************
- ** This is an auto-generated file **
- ** DO NOT EDIT BELOW **
- ************************************/
-
-#ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_
-#define ASIC_REG_XBAR_EDGE_0_REGS_H_
-
-/*
- *****************************************
- * XBAR_EDGE_0
- * (Prototype: XBAR)
- *****************************************
- */
-
-#define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000
-
-#define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004
-
-#define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008
-
-#define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C
-
-#define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010
-
-#define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014
-
-#define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018
-
-#define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C
-
-#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020
-
-#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024
-
-#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028
-
-#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C
-
-#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030
-
-#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034
-
-#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038
-
-#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C
-
-#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040
-
-#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044
-
-#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048
-
-#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C
-
-#define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080
-
-#define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084
-
-#define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088
-
-#define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C
-
-#define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090
-
-#define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094
-
-#define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098
-
-#define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C
-
-#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0
-
-#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4
-
-#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8
-
-#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC
-
-#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0
-
-#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4
-
-#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8
-
-#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC
-
-#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0
-
-#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4
-
-#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8
-
-#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC
-
-#define mmXBAR_EDGE_0_LBW_INTERNAL_ADDR_RGF 0x4D480D0
-
-#define mmXBAR_EDGE_0_DBG_INTERNAL_ADDR_FUN 0x4D480D4
-
-#define mmXBAR_EDGE_0_EMEM_HBM_BIT_LOCATION 0x4D48100
-
-#define mmXBAR_EDGE_0_EMEM_PC_BIT_LOCATION 0x4D48104
-
-#define mmXBAR_EDGE_0_HIF_WR_RS_CH_LOCATION 0x4D48108
-
-#define mmXBAR_EDGE_0_HBW_MST_ARB_WEIGHT 0x4D4810C
-
-#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_0 0x4D48110
-
-#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_1 0x4D48114
-
-#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_0 0x4D48120
-
-#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_1 0x4D48124
-
-#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_0 0x4D48128
-
-#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_1 0x4D4812C
-
-#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_0 0x4D48130
-
-#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_1 0x4D48134
-
-#define mmXBAR_EDGE_0_RL_RD_0 0x4D48140
-
-#define mmXBAR_EDGE_0_RL_RD_1 0x4D48144
-
-#define mmXBAR_EDGE_0_RL_RD_2 0x4D48148
-
-#define mmXBAR_EDGE_0_RL_RD_3 0x4D4814C
-
-#define mmXBAR_EDGE_0_RL_RD_4 0x4D48150
-
-#define mmXBAR_EDGE_0_RL_RD_5 0x4D48154
-
-#define mmXBAR_EDGE_0_RL_RD_6 0x4D48158
-
-#define mmXBAR_EDGE_0_RL_RD_7 0x4D4815C
-
-#define mmXBAR_EDGE_0_RL_RD_8 0x4D48160
-
-#define mmXBAR_EDGE_0_RL_RD_9 0x4D48164
-
-#define mmXBAR_EDGE_0_RL_RD_10 0x4D48168
-
-#define mmXBAR_EDGE_0_RL_RD_11 0x4D4816C
-
-#define mmXBAR_EDGE_0_RL_WR_0 0x4D48180
-
-#define mmXBAR_EDGE_0_RL_WR_1 0x4D48184
-
-#define mmXBAR_EDGE_0_RL_WR_2 0x4D48188
-
-#define mmXBAR_EDGE_0_RL_WR_3 0x4D4818C
-
-#define mmXBAR_EDGE_0_RL_WR_4 0x4D48190
-
-#define mmXBAR_EDGE_0_RL_WR_5 0x4D48194
-
-#define mmXBAR_EDGE_0_RL_WR_6 0x4D48198
-
-#define mmXBAR_EDGE_0_RL_WR_7 0x4D4819C
-
-#define mmXBAR_EDGE_0_RL_WR_8 0x4D481A0
-
-#define mmXBAR_EDGE_0_RL_WR_9 0x4D481A4
-
-#define mmXBAR_EDGE_0_RL_WR_10 0x4D481A8
-
-#define mmXBAR_EDGE_0_RL_WR_11 0x4D481AC
-
-#define mmXBAR_EDGE_0_E2E_CRDT_SLV_0 0x4D481B0
-
-#define mmXBAR_EDGE_0_E2E_CRDT_SLV_1 0x4D481B4
-
-#define mmXBAR_EDGE_0_E2E_CRDT_SLV_2 0x4D481B8
-
-#define mmXBAR_EDGE_0_E2E_CRDT_DEBUG 0x4D481BC
-
-#define mmXBAR_EDGE_0_UPSCALE 0x4D481C0
-
-#define mmXBAR_EDGE_0_DOWN_CONV 0x4D481C4
-
-#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN 0x4D481D0
-
-#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD 0x4D481D4
-
-#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE 0x4D481D8
-
-#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY 0x4D481DC
-
-#endif /* ASIC_REG_XBAR_EDGE_0_REGS_H_ */
projects / linux-2.6-microblaze.git / blobdiff