+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright 2016-2018 HabanaLabs, Ltd.
- * All Rights Reserved.
- *
- */
-
-/************************************
- ** This is an auto-generated file **
- ** DO NOT EDIT BELOW **
- ************************************/
-
-#ifndef ASIC_REG_TPC5_CFG_REGS_H_
-#define ASIC_REG_TPC5_CFG_REGS_H_
-
-/*
- *****************************************
- * TPC5_CFG (Prototype: TPC)
- *****************************************
- */
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430
-
-#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468
-
-#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510
-
-#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548
-
-#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580
-
-#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628
-
-#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660
-
-#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698
-
-#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708
-
-#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740
-
-#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778
-
-#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C
-
-#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780
-
-#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784
-
-#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788
-
-#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C
-
-#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790
-
-#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794
-
-#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798
-
-#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C
-
-#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0
-
-#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4
-
-#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8
-
-#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC
-
-#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0
-
-#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4
-
-#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8
-
-#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC
-
-#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0
-
-#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4
-
-#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8
-
-#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC
-
-#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0
-
-#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4
-
-#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8
-
-#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC
-
-#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0
-
-#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4
-
-#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8
-
-#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC
-
-#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0
-
-#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4
-
-#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8
-
-#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC
-
-#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800
-
-#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804
-
-#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808
-
-#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C
-
-#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810
-
-#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814
-
-#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818
-
-#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C
-
-#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820
-
-#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824
-
-#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828
-
-#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C
-
-#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830
-
-#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834
-
-#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838
-
-#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C
-
-#define mmTPC5_CFG_ROUND_CSR 0xF468FC
-
-#define mmTPC5_CFG_PROT 0xF46900
-
-#define mmTPC5_CFG_SEMAPHORE 0xF46908
-
-#define mmTPC5_CFG_VFLAGS 0xF4690C
-
-#define mmTPC5_CFG_SFLAGS 0xF46910
-
-#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918
-
-#define mmTPC5_CFG_STATUS 0xF4691C
-
-#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920
-
-#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924
-
-#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C
-
-#define mmTPC5_CFG_TPC_CMD 0xF46930
-
-#define mmTPC5_CFG_TPC_EXECUTE 0xF46938
-
-#define mmTPC5_CFG_TPC_STALL 0xF4693C
-
-#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940
-
-#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944
-
-#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948
-
-#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950
-
-#define mmTPC5_CFG_MSS_CONFIG 0xF46954
-
-#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958
-
-#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C
-
-#define mmTPC5_CFG_WQ_CREDITS 0xF46960
-
-#define mmTPC5_CFG_ARUSER_LO 0xF46964
-
-#define mmTPC5_CFG_ARUSER_HI 0xF46968
-
-#define mmTPC5_CFG_AWUSER_LO 0xF4696C
-
-#define mmTPC5_CFG_AWUSER_HI 0xF46970
-
-#define mmTPC5_CFG_OPCODE_EXEC 0xF46974
-
-#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978
-
-#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C
-
-#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980
-
-#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984
-
-#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988
-
-#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C
-
-#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990
-
-#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994
-
-#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998
-
-#define mmTPC5_CFG_TSB_CFG 0xF4699C
-
-#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0
-
-#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4
-
-#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8
-
-#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC
-
-#define mmTPC5_CFG_DBGMEM_RC 0xF469B0
-
-#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4
-
-#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8
-
-#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC
-
-#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0
-
-#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4
-
-#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0
-
-#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8
-
-#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC
-
-#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00
-
-#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04
-
-#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08
-
-#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30
-
-#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34
-
-#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38
-
-#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C
-
-#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40
-
-#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68
-
-#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C
-
-#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70
-
-#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74
-
-#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78
-
-#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0
-
-#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4
-
-#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8
-
-#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC
-
-#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0
-
-#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8
-
-#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC
-
-#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0
-
-#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4
-
-#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8
-
-#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10
-
-#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14
-
-#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18
-
-#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C
-
-#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20
-
-#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48
-
-#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C
-
-#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50
-
-#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54
-
-#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58
-
-#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80
-
-#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84
-
-#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88
-
-#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C
-
-#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90
-
-#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8
-
-#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC
-
-#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0
-
-#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4
-
-#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8
-
-#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0
-
-#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4
-
-#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8
-
-#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC
-
-#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00
-
-#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28
-
-#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C
-
-#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30
-
-#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34
-
-#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38
-
-#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60
-
-#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64
-
-#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68
-
-#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C
-
-#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70
-
-#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98
-
-#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C
-
-#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0
-
-#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4
-
-#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8
-
-#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0
-
-#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4
-
-#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8
-
-#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC
-
-#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0
-
-#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08
-
-#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C
-
-#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10
-
-#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14
-
-#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18
-
-#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40
-
-#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44
-
-#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48
-
-#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C
-
-#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50
-
-#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78
-
-#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C
-
-#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80
-
-#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84
-
-#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88
-
-#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C
-
-#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90
-
-#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94
-
-#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98
-
-#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C
-
-#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0
-
-#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4
-
-#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8
-
-#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC
-
-#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0
-
-#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4
-
-#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8
-
-#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC
-
-#define mmTPC5_CFG_QM_SRF_0 0xF46DC0
-
-#define mmTPC5_CFG_QM_SRF_1 0xF46DC4
-
-#define mmTPC5_CFG_QM_SRF_2 0xF46DC8
-
-#define mmTPC5_CFG_QM_SRF_3 0xF46DCC
-
-#define mmTPC5_CFG_QM_SRF_4 0xF46DD0
-
-#define mmTPC5_CFG_QM_SRF_5 0xF46DD4
-
-#define mmTPC5_CFG_QM_SRF_6 0xF46DD8
-
-#define mmTPC5_CFG_QM_SRF_7 0xF46DDC
-
-#define mmTPC5_CFG_QM_SRF_8 0xF46DE0
-
-#define mmTPC5_CFG_QM_SRF_9 0xF46DE4
-
-#define mmTPC5_CFG_QM_SRF_10 0xF46DE8
-
-#define mmTPC5_CFG_QM_SRF_11 0xF46DEC
-
-#define mmTPC5_CFG_QM_SRF_12 0xF46DF0
-
-#define mmTPC5_CFG_QM_SRF_13 0xF46DF4
-
-#define mmTPC5_CFG_QM_SRF_14 0xF46DF8
-
-#define mmTPC5_CFG_QM_SRF_15 0xF46DFC
-
-#define mmTPC5_CFG_QM_SRF_16 0xF46E00
-
-#define mmTPC5_CFG_QM_SRF_17 0xF46E04
-
-#define mmTPC5_CFG_QM_SRF_18 0xF46E08
-
-#define mmTPC5_CFG_QM_SRF_19 0xF46E0C
-
-#define mmTPC5_CFG_QM_SRF_20 0xF46E10
-
-#define mmTPC5_CFG_QM_SRF_21 0xF46E14
-
-#define mmTPC5_CFG_QM_SRF_22 0xF46E18
-
-#define mmTPC5_CFG_QM_SRF_23 0xF46E1C
-
-#define mmTPC5_CFG_QM_SRF_24 0xF46E20
-
-#define mmTPC5_CFG_QM_SRF_25 0xF46E24
-
-#define mmTPC5_CFG_QM_SRF_26 0xF46E28
-
-#define mmTPC5_CFG_QM_SRF_27 0xF46E2C
-
-#define mmTPC5_CFG_QM_SRF_28 0xF46E30
-
-#define mmTPC5_CFG_QM_SRF_29 0xF46E34
-
-#define mmTPC5_CFG_QM_SRF_30 0xF46E38
-
-#define mmTPC5_CFG_QM_SRF_31 0xF46E3C
-
-#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */
projects / linux-2.6-microblaze.git / blobdiff