media: camss: use v4l2_get_link_freq() to calculate the relevant clocks

[linux-2.6-microblaze.git] / drivers / media / platform / qcom / camss / camss-csiphy.c

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index 509c9a5..40384d7 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -102,23 +102,23 @@ static u8 csiphy_get_bpp(const struct csiphy_format *formats,
 static int csiphy_set_clock_rates(struct csiphy_device *csiphy)
 {
        struct device *dev = csiphy->camss->dev;
-       u32 pixel_clock;
+       s64 link_freq;
        int i, j;
        int ret;
 
-       ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
-       if (ret)
-               pixel_clock = 0;
+       u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats,
+                               csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
+       u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
+
+       link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+       if (link_freq < 0)
+               link_freq  = 0;
 
        for (i = 0; i < csiphy->nclocks; i++) {
                struct camss_clock *clock = &csiphy->clock[i];
 
                if (csiphy->rate_set[i]) {
-                       u8 bpp = csiphy_get_bpp(csiphy->formats,
-                                       csiphy->nformats,
-                                       csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
-                       u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
-                       u64 min_rate = pixel_clock * bpp / (2 * num_lanes * 4);
+                       u64 min_rate = link_freq / 4;
                        long round_rate;
 
                        camss_add_clock_margin(&min_rate);
@@ -238,22 +238,18 @@ static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
 static int csiphy_stream_on(struct csiphy_device *csiphy)
 {
        struct csiphy_config *cfg = &csiphy->cfg;
-       u32 pixel_clock;
+       s64 link_freq;
        u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg);
        u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats,
                                csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
+       u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
        u8 val;
-       int ret;
 
-       ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
-       if (ret) {
-               dev_err(csiphy->camss->dev,
-                       "Cannot get CSI2 transmitter's pixel clock\n");
-               return -EINVAL;
-       }
-       if (!pixel_clock) {
+       link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+
+       if (link_freq < 0) {
                dev_err(csiphy->camss->dev,
-                       "Got pixel clock == 0, cannot continue\n");
+                       "Cannot get CSI2 transmitter's link frequency\n");
                return -EINVAL;
        }
 
@@ -268,7 +264,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
        writel_relaxed(val, csiphy->base_clk_mux);
        wmb();
 
-       csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask);
+       csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask);
 
        return 0;
 }