media: atmel: atmel-isc: add his_entry to register offsets

[linux-2.6-microblaze.git] / drivers / media / platform / atmel / atmel-isc-base.c

diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
index ed0048e..cfe60b2 100644 (file)
--- a/drivers/media/platform/atmel/atmel-isc-base.c
+++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw *hw)
        unsigned long flags;
        unsigned int status;
 
-       dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
-               __func__, isc_clk->div, isc_clk->parent_id);
+       dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
+               __func__, id, isc_clk->div, isc_clk->parent_id);
 
        spin_lock_irqsave(&isc_clk->lock, flags);
        regmap_update_bits(regmap, ISC_CLKCFG,
@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_device *isc)
                           ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 
        addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
-       regmap_write(regmap, ISC_DAD0, addr0);
+       regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
 
        switch (isc->config.fourcc) {
        case V4L2_PIX_FMT_YUV420:
-               regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
-               regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
+               regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
+                            addr0 + (sizeimage * 2) / 3);
+               regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
+                            addr0 + (sizeimage * 5) / 6);
                break;
        case V4L2_PIX_FMT_YUV422P:
-               regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
-               regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
+               regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
+                            addr0 + sizeimage / 2);
+               regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
+                            addr0 + (sizeimage * 3) / 4);
                break;
        default:
                break;
@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_device *isc)
 
        dctrl_dview = isc->config.dctrl_dview;
 
-       regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
+       regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
+                    dctrl_dview | ISC_DCTRL_IE_IS);
        spin_lock(&isc->awb_lock);
        regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
        spin_unlock(&isc->awb_lock);
@@ -654,16 +659,8 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
        regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
        regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 
-       /* Convert RGB to YUV */
-       regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
-       regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
-       regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
-       regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
-       regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
-       regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
-
-       regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
-       regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
+       isc->config_csc(isc);
+       isc->config_cbc(isc);
 }
 
 static int isc_update_profile(struct isc_device *isc)
@@ -694,12 +691,13 @@ static void isc_set_histogram(struct isc_device *isc, bool enable)
        struct isc_ctrls *ctrls = &isc->ctrls;
 
        if (enable) {
-               regmap_write(regmap, ISC_HIS_CFG,
+               regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
                             ISC_HIS_CFG_MODE_GR |
                             (isc->config.sd_format->cfa_baycfg
                                        << ISC_HIS_CFG_BAYSEL_SHIFT) |
                                        ISC_HIS_CFG_RAR);
-               regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
+               regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
+                            ISC_HIS_CTRL_EN);
                regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
                ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
                isc_update_profile(isc);
@@ -708,7 +706,8 @@ static void isc_set_histogram(struct isc_device *isc, bool enable)
                ctrls->hist_stat = HIST_ENABLED;
        } else {
                regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
-               regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
+               regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
+                            ISC_HIS_CTRL_DIS);
 
                ctrls->hist_stat = HIST_DISABLED;
        }
@@ -724,8 +723,7 @@ static int isc_configure(struct isc_device *isc)
        rlp_mode = isc->config.rlp_cfg_mode;
        pipeline = isc->config.bits_pipeline;
 
-       dcfg = isc->config.dcfg_imode |
-                      ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+       dcfg = isc->config.dcfg_imode | isc->dcfg;
 
        pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
        mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
@@ -735,10 +733,10 @@ static int isc_configure(struct isc_device *isc)
 
        regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 
-       regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
-                          rlp_mode);
+       regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
+                          ISC_RLP_CFG_MODE_MASK, rlp_mode);
 
-       regmap_write(regmap, ISC_DCFG, dcfg);
+       regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 
        /* Set the pipeline */
        isc_set_pipeline(isc, pipeline);
@@ -1686,7 +1684,8 @@ static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
        *min = 0;
        *max = HIST_ENTRIES;
 
-       regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
+       regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
+                        hist_entry, HIST_ENTRIES);
 
        *hist_count = 0;
        /*
@@ -1845,7 +1844,8 @@ static void isc_awb_work(struct work_struct *w)
                        ctrls->awb = ISC_WB_NONE;
                }
        }
-       regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
+       regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
+                    hist_id | baysel | ISC_HIS_CFG_RAR);
        isc_update_profile(isc);
        /* if awb has been disabled, we don't need to start another histogram */
        if (ctrls->awb)
@@ -2333,10 +2333,10 @@ int isc_pipeline_init(struct isc_device *isc)
                REG_FIELD(ISC_GAM_CTRL, 1, 1),
                REG_FIELD(ISC_GAM_CTRL, 2, 2),
                REG_FIELD(ISC_GAM_CTRL, 3, 3),
-               REG_FIELD(ISC_CSC_CTRL, 0, 0),
-               REG_FIELD(ISC_CBC_CTRL, 0, 0),
-               REG_FIELD(ISC_SUB422_CTRL, 0, 0),
-               REG_FIELD(ISC_SUB420_CTRL, 0, 0),
+               REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
+               REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
+               REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
+               REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
        };
 
        for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {