pinctrl: qcom: ipq6018 Add missing pins in qpic pin group

[linux-2.6-microblaze.git] / drivers / iommu / arm-smmu-v3.c

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 42e1ee7..f578677 100644 (file)
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -171,6 +171,8 @@
 #define ARM_SMMU_PRIQ_IRQ_CFG1         0xd8
 #define ARM_SMMU_PRIQ_IRQ_CFG2         0xdc
 
+#define ARM_SMMU_REG_SZ                        0xe00
+
 /* Common MSI config fields */
 #define MSI_CFG0_ADDR_MASK             GENMASK_ULL(51, 2)
 #define MSI_CFG2_SH                    GENMASK(5, 4)
@@ -628,6 +630,7 @@ struct arm_smmu_strtab_cfg {
 struct arm_smmu_device {
        struct device                   *dev;
        void __iomem                    *base;
+       void __iomem                    *page1;
 
 #define ARM_SMMU_FEAT_2_LVL_STRTAB     (1 << 0)
 #define ARM_SMMU_FEAT_2_LVL_CDTAB      (1 << 1)
@@ -664,7 +667,6 @@ struct arm_smmu_device {
 
 #define ARM_SMMU_MAX_ASIDS             (1 << 16)
        unsigned int                    asid_bits;
-       DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS);
 
 #define ARM_SMMU_MAX_VMIDS             (1 << 16)
        unsigned int                    vmid_bits;
@@ -724,6 +726,8 @@ struct arm_smmu_option_prop {
        const char *prop;
 };
 
+static DEFINE_XARRAY_ALLOC1(asid_xa);
+
 static struct arm_smmu_option_prop arm_smmu_options[] = {
        { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
        { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
@@ -733,9 +737,8 @@ static struct arm_smmu_option_prop arm_smmu_options[] = {
 static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset,
                                                 struct arm_smmu_device *smmu)
 {
-       if ((offset > SZ_64K) &&
-           (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY))
-               offset -= SZ_64K;
+       if (offset > SZ_64K)
+               return smmu->page1 + offset - SZ_64K;
 
        return smmu->base + offset;
 }
@@ -1763,6 +1766,14 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain)
        cdcfg->cdtab = NULL;
 }
 
+static void arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)
+{
+       if (!cd->asid)
+               return;
+
+       xa_erase(&asid_xa, cd->asid);
+}
+
 /* Stream table manipulation functions */
 static void
 arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
@@ -2448,10 +2459,9 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)
        if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
                struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
 
-               if (cfg->cdcfg.cdtab) {
+               if (cfg->cdcfg.cdtab)
                        arm_smmu_free_cd_tables(smmu_domain);
-                       arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid);
-               }
+               arm_smmu_free_asid(&cfg->cd);
        } else {
                struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
                if (cfg->vmid)
@@ -2466,14 +2476,15 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
                                       struct io_pgtable_cfg *pgtbl_cfg)
 {
        int ret;
-       int asid;
+       u32 asid;
        struct arm_smmu_device *smmu = smmu_domain->smmu;
        struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
        typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr;
 
-       asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits);
-       if (asid < 0)
-               return asid;
+       ret = xa_alloc(&asid_xa, &asid, &cfg->cd,
+                      XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
+       if (ret)
+               return ret;
 
        cfg->s1cdmax = master->ssid_bits;
 
@@ -2506,7 +2517,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
 out_free_cd_tables:
        arm_smmu_free_cd_tables(smmu_domain);
 out_free_asid:
-       arm_smmu_bitmap_free(smmu->asid_map, asid);
+       arm_smmu_free_asid(&cfg->cd);
        return ret;
 }
 
@@ -2652,26 +2663,20 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
        }
 }
 
-#ifdef CONFIG_PCI_ATS
 static bool arm_smmu_ats_supported(struct arm_smmu_master *master)
 {
-       struct pci_dev *pdev;
+       struct device *dev = master->dev;
        struct arm_smmu_device *smmu = master->smmu;
-       struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev);
+       struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 
-       if (!(smmu->features & ARM_SMMU_FEAT_ATS) || !dev_is_pci(master->dev) ||
-           !(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS) || pci_ats_disabled())
+       if (!(smmu->features & ARM_SMMU_FEAT_ATS))
                return false;
 
-       pdev = to_pci_dev(master->dev);
-       return !pdev->untrusted && pdev->ats_cap;
-}
-#else
-static bool arm_smmu_ats_supported(struct arm_smmu_master *master)
-{
-       return false;
+       if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS))
+               return false;
+
+       return dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev));
 }
-#endif
 
 static void arm_smmu_enable_ats(struct arm_smmu_master *master)
 {
@@ -2986,13 +2991,11 @@ static void arm_smmu_release_device(struct device *dev)
 {
        struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
        struct arm_smmu_master *master;
-       struct arm_smmu_device *smmu;
 
        if (!fwspec || fwspec->ops != &arm_smmu_ops)
                return;
 
        master = dev_iommu_priv_get(dev);
-       smmu = master->smmu;
        arm_smmu_detach_dev(master);
        arm_smmu_disable_pasid(master);
        kfree(master);
@@ -4003,6 +4006,18 @@ err_reset_pci_ops: __maybe_unused;
        return err;
 }
 
+static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start,
+                                     resource_size_t size)
+{
+       struct resource res = {
+               .flags = IORESOURCE_MEM,
+               .start = start,
+               .end = start + size - 1,
+       };
+
+       return devm_ioremap_resource(dev, &res);
+}
+
 static int arm_smmu_device_probe(struct platform_device *pdev)
 {
        int irq, ret;
@@ -4038,10 +4053,23 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
        }
        ioaddr = res->start;
 
-       smmu->base = devm_ioremap_resource(dev, res);
+       /*
+        * Don't map the IMPLEMENTATION DEFINED regions, since they may contain
+        * the PMCG registers which are reserved by the PMU driver.
+        */
+       smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
        if (IS_ERR(smmu->base))
                return PTR_ERR(smmu->base);
 
+       if (arm_smmu_resource_size(smmu) > SZ_64K) {
+               smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
+                                              ARM_SMMU_REG_SZ);
+               if (IS_ERR(smmu->page1))
+                       return PTR_ERR(smmu->page1);
+       } else {
+               smmu->page1 = smmu->base;
+       }
+
        /* Interrupt lines */
 
        irq = platform_get_irq_byname_optional(pdev, "combined");