Merge branches 'iommu/fixes', 'arm/mediatek', 'arm/smmu', 'arm/exynos', 'unisoc'...

[linux-2.6-microblaze.git] / drivers / iommu / amd / init.c

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 321f590..54f6e99 100644 (file)
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -12,7 +12,6 @@
 #include <linux/acpi.h>
 #include <linux/list.h>
 #include <linux/bitmap.h>
-#include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/syscore_ops.h>
 #include <linux/interrupt.h>
@@ -208,7 +207,6 @@ u16 *amd_iommu_alias_table;
  * for a specific device. It is also indexed by the PCI device id.
  */
 struct amd_iommu **amd_iommu_rlookup_table;
-EXPORT_SYMBOL(amd_iommu_rlookup_table);
 
 /*
  * This table is used to find the irq remapping table for a given device id
@@ -257,8 +255,6 @@ static enum iommu_init_state init_state = IOMMU_START_STATE;
 static int amd_iommu_enable_interrupts(void);
 static int __init iommu_go_to_state(enum iommu_init_state state);
 static void init_device_table_dma(void);
-static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
-                               u8 fxn, u64 *value, bool is_write);
 
 static bool amd_iommu_pre_enabled = true;
 
@@ -268,7 +264,6 @@ bool translation_pre_enabled(struct amd_iommu *iommu)
 {
        return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
 }
-EXPORT_SYMBOL(translation_pre_enabled);
 
 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
 {
@@ -1717,53 +1712,16 @@ static int __init init_iommu_all(struct acpi_table_header *table)
        return 0;
 }
 
-static void __init init_iommu_perf_ctr(struct amd_iommu *iommu)
+static void init_iommu_perf_ctr(struct amd_iommu *iommu)
 {
-       int retry;
+       u64 val;
        struct pci_dev *pdev = iommu->dev;
-       u64 val = 0xabcd, val2 = 0, save_reg, save_src;
 
        if (!iommu_feature(iommu, FEATURE_PC))
                return;
 
        amd_iommu_pc_present = true;
 
-       /* save the value to restore, if writable */
-       if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false) ||
-           iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, false))
-               goto pc_false;
-
-       /*
-        * Disable power gating by programing the performance counter
-        * source to 20 (i.e. counts the reads and writes from/to IOMMU
-        * Reserved Register [MMIO Offset 1FF8h] that are ignored.),
-        * which never get incremented during this init phase.
-        * (Note: The event is also deprecated.)
-        */
-       val = 20;
-       if (iommu_pc_get_set_reg(iommu, 0, 0, 8, &val, true))
-               goto pc_false;
-
-       /* Check if the performance counters can be written to */
-       val = 0xabcd;
-       for (retry = 5; retry; retry--) {
-               if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true) ||
-                   iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false) ||
-                   val2)
-                       break;
-
-               /* Wait about 20 msec for power gating to disable and retry. */
-               msleep(20);
-       }
-
-       /* restore */
-       if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true) ||
-           iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, true))
-               goto pc_false;
-
-       if (val != val2)
-               goto pc_false;
-
        pci_info(pdev, "IOMMU performance counters supported\n");
 
        val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
@@ -1771,11 +1729,6 @@ static void __init init_iommu_perf_ctr(struct amd_iommu *iommu)
        iommu->max_counters = (u8) ((val >> 7) & 0xf);
 
        return;
-
-pc_false:
-       pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n");
-       amd_iommu_pc_present = false;
-       return;
 }
 
 static ssize_t amd_iommu_show_cap(struct device *dev,
@@ -1837,7 +1790,7 @@ static void __init late_iommu_features_init(struct amd_iommu *iommu)
         * IVHD and MMIO conflict.
         */
        if (features != iommu->features)
-               pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx\n).",
+               pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n",
                        features, iommu->features);
 }
 
@@ -3277,7 +3230,6 @@ struct amd_iommu *get_amd_iommu(unsigned int idx)
                        return iommu;
        return NULL;
 }
-EXPORT_SYMBOL(get_amd_iommu);
 
 /****************************************************************************
  *
@@ -3359,7 +3311,6 @@ int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64
 
        return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
 }
-EXPORT_SYMBOL(amd_iommu_pc_get_reg);
 
 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
 {
@@ -3368,4 +3319,3 @@ int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64
 
        return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
 }
-EXPORT_SYMBOL(amd_iommu_pc_set_reg);