Merge tag 'v5.16' into rdma.git for-next

[linux-2.6-microblaze.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index eb0defa..b33e948 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -678,6 +678,7 @@ static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
                       void *wqe)
 {
+#define HNS_ROCE_SL_SHIFT 2
        struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 
        /* All kinds of DirectWQE have the same header field layout */
@@ -685,7 +686,8 @@ static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
        roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M,
                       V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl);
        roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M,
-                      V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2);
+                      V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S,
+                      qp->sl >> HNS_ROCE_SL_SHIFT);
        roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M,
                       V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head);
 
@@ -1305,14 +1307,14 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
                                continue;
 
                        dev_err_ratelimited(hr_dev->dev,
-                                           "Cmdq IO error, opcode = %x, return = %x\n",
+                                           "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
                                            desc->opcode, desc_ret);
                        ret = -EIO;
                }
        } else {
                /* FW/HW reset or incorrect number of desc */
                tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
-               dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n",
+               dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
                         csq->head, tail);
                csq->head = tail;
 
@@ -1571,7 +1573,7 @@ static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
        struct hns_roce_cmq_desc desc;
        int ret;
 
-       if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) {
+       if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
                hr_dev->func_num = 1;
                return 0;
        }
@@ -2003,7 +2005,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
        caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
 
        if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
-               caps->flags |= HNS_ROCE_CAP_FLAG_STASH;
+               caps->flags |= HNS_ROCE_CAP_FLAG_STASH |
+                              HNS_ROCE_CAP_FLAG_DIRECT_WQE;
                caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;
        } else {
                caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
@@ -2144,7 +2147,6 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)
        caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
        caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
 
-       caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
        caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
        caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
        caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
@@ -2161,6 +2163,7 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)
                                  (u32)priv->handle->rinfo.num_vectors - 2);
 
        if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
+               caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
                caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
                caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
 
@@ -2181,6 +2184,7 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)
        } else {
                u32 func_num = max_t(u32, 1, hr_dev->func_num);
 
+               caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
                caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
                caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
                caps->gid_table_len[0] /= func_num;
@@ -2393,7 +2397,7 @@ static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
        struct hns_roce_caps *caps = &hr_dev->caps;
        int ret;
 
-       if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09)
+       if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
                return 0;
 
        ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
@@ -2967,8 +2971,8 @@ static int config_gmv_table(struct hns_roce_dev *hr_dev,
        return hns_roce_cmq_send(hr_dev, desc, 2);
 }
 
-static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u32 port,
-                              int gid_index, const union ib_gid *gid,
+static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
+                              const union ib_gid *gid,
                               const struct ib_gid_attr *attr)
 {
        enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
@@ -3063,8 +3067,7 @@ static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
 }
 
 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
-                                 void *mb_buf, struct hns_roce_mr *mr,
-                                 unsigned long mtpt_idx)
+                                 void *mb_buf, struct hns_roce_mr *mr)
 {
        struct hns_roce_v2_mpt_entry *mpt_entry;
        int ret;
@@ -4488,14 +4491,6 @@ static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
        return 0;
 }
 
-static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn)
-{
-       if (!fl)
-               fl = rdma_calc_flow_label(lqpn, rqpn);
-
-       return rdma_flow_label_to_udp_sport(fl);
-}
-
 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
                           u32 *dip_idx)
 {
@@ -4712,8 +4707,9 @@ static int hns_roce_v2_set_path(struct ib_qp *ibqp,
        }
 
        hr_reg_write(context, QPC_UDPSPN,
-                    is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num,
-                                           attr->dest_qp_num) : 0);
+                    is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
+                                                attr->dest_qp_num) :
+                                   0);
 
        hr_reg_clear(qpc_mask, QPC_UDPSPN);
 
@@ -4739,7 +4735,7 @@ static int hns_roce_v2_set_path(struct ib_qp *ibqp,
        hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
        if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) {
                ibdev_err(ibdev,
-                         "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n",
+                         "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n",
                          hr_qp->sl, MAX_SERVICE_LEVEL);
                return -EINVAL;
        }
@@ -4768,7 +4764,8 @@ static bool check_qp_state(enum ib_qp_state cur_state,
                                 [IB_QPS_ERR] = true },
                [IB_QPS_SQD] = {},
                [IB_QPS_SQE] = {},
-               [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
+               [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
+                                [IB_QPS_ERR] = true }
        };
 
        return sm[cur_state][new_state];
@@ -5868,7 +5865,7 @@ static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
        roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
 }
 
-static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
+static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)
 {
        struct device *dev = hr_dev->dev;
        int ret;
@@ -5882,7 +5879,7 @@ static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
                                        0, HNS_ROCE_CMD_DESTROY_AEQC,
                                        HNS_ROCE_CMD_TIMEOUT_MSECS);
        if (ret)
-               dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
+               dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
 }
 
 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
@@ -6394,7 +6391,7 @@ static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
        if (!id)
                return 0;
 
-       if (id->driver_data && handle->pdev->revision < PCI_REVISION_ID_HIP09)
+       if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
                return 0;
 
        ret = __hns_roce_hw_v2_init_instance(handle);