RDMA/hns: Remove unused RR mechanism

[linux-2.6-microblaze.git] / drivers / infiniband / hw / hns / hns_roce_hw_v1.c

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
index 620acf6..4045d59 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -462,6 +462,81 @@ static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
        roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 }
 
+static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
+                              struct hns_roce_hem_table *table, int obj,
+                              int step_idx)
+{
+       spinlock_t *lock = &hr_dev->bt_cmd_lock;
+       struct device *dev = hr_dev->dev;
+       struct hns_roce_hem_iter iter;
+       void __iomem *bt_cmd;
+       __le32 bt_cmd_val[2];
+       __le32 bt_cmd_h = 0;
+       unsigned long flags;
+       __le32 bt_cmd_l;
+       int ret = 0;
+       u64 bt_ba;
+       long end;
+
+       /* Find the HEM(Hardware Entry Memory) entry */
+       unsigned long i = obj / (table->table_chunk_size / table->obj_size);
+
+       switch (table->type) {
+       case HEM_TYPE_QPC:
+       case HEM_TYPE_MTPT:
+       case HEM_TYPE_CQC:
+       case HEM_TYPE_SRQC:
+               roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
+                       ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
+               break;
+       default:
+               return ret;
+       }
+
+       roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
+                      ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
+       roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
+       roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
+
+       /* Currently iter only a chunk */
+       for (hns_roce_hem_first(table->hem[i], &iter);
+            !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
+               bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
+
+               spin_lock_irqsave(lock, flags);
+
+               bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
+
+               end = HW_SYNC_TIMEOUT_MSECS;
+               while (end > 0) {
+                       if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
+                               break;
+
+                       mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
+                       end -= HW_SYNC_SLEEP_TIME_INTERVAL;
+               }
+
+               if (end <= 0) {
+                       dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
+                       spin_unlock_irqrestore(lock, flags);
+                       return -EBUSY;
+               }
+
+               bt_cmd_l = cpu_to_le32(bt_ba);
+               roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
+                              ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
+                              upper_32_bits(bt_ba));
+
+               bt_cmd_val[0] = bt_cmd_l;
+               bt_cmd_val[1] = bt_cmd_h;
+               hns_roce_write64_k(bt_cmd_val,
+                                  hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
+               spin_unlock_irqrestore(lock, flags);
+       }
+
+       return ret;
+}
+
 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
                                     u32 odb_mode)
 {
@@ -1124,7 +1199,7 @@ free_mr:
                mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
 
        hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
-                            key_to_hw_index(mr->key), 0);
+                            key_to_hw_index(mr->key));
        hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
        kfree(mr);
 
@@ -4352,6 +4427,7 @@ static const struct hns_roce_hw hns_roce_hw_v1 = {
        .set_mtu = hns_roce_v1_set_mtu,
        .write_mtpt = hns_roce_v1_write_mtpt,
        .write_cqc = hns_roce_v1_write_cqc,
+       .set_hem = hns_roce_v1_set_hem,
        .clear_hem = hns_roce_v1_clear_hem,
        .modify_qp = hns_roce_v1_modify_qp,
        .dereg_mr = hns_roce_v1_dereg_mr,