static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
- int regval, timeout = 10000;
+ int val;
/*
* NOTE: we need a small delay before reading the status, otherwise
* the sample engine may not have started internally (which would
* seem to us that sampling is already finished).
*/
- do {
- udelay(1);
- regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
- } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
-
- if (timeout < 0)
- return -ETIMEDOUT;
-
- return 0;
+ udelay(1);
+ return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,
+ !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),
+ 1, 10000);
}
static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
int *val)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
int regval, fifo_chan, fifo_val, count;
if (!wait_for_completion_timeout(&priv->done,
count = meson_sar_adc_get_fifo_count(indio_dev);
if (count != 1) {
- dev_err(&indio_dev->dev,
- "ADC FIFO has %d element(s) instead of one\n", count);
+ dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);
return -EINVAL;
}
regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
if (fifo_chan != chan->address) {
- dev_err(&indio_dev->dev,
- "ADC FIFO entry belongs to channel %d instead of %lu\n",
+ dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",
fifo_chan, chan->address);
return -EINVAL;
}
static int meson_sar_adc_lock(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
- int val, timeout = 10000;
+ int val, ret;
mutex_lock(&indio_dev->mlock);
MESON_SAR_ADC_DELAY_KERNEL_BUSY,
MESON_SAR_ADC_DELAY_KERNEL_BUSY);
+ udelay(1);
+
/*
* wait until BL30 releases it's lock (so we can use the SAR
* ADC)
*/
- do {
- udelay(1);
- regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
- } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
-
- if (timeout < 0) {
+ ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,
+ !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),
+ 1, 10000);
+ if (ret) {
mutex_unlock(&indio_dev->mlock);
- return -ETIMEDOUT;
+ return ret;
}
}
int *val)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
int ret;
if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
meson_sar_adc_unlock(indio_dev);
if (ret) {
- dev_warn(indio_dev->dev.parent,
- "failed to read sample for channel %lu: %d\n",
+ dev_warn(dev, "failed to read sample for channel %lu: %d\n",
chan->address, ret);
return ret;
}
int *val, int *val2, long mask)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
int ret;
switch (mask) {
if (chan->type == IIO_VOLTAGE) {
ret = regulator_get_voltage(priv->vref);
if (ret < 0) {
- dev_err(indio_dev->dev.parent,
- "failed to get vref voltage: %d\n",
- ret);
+ dev_err(dev, "failed to get vref voltage: %d\n", ret);
return ret;
}
void __iomem *base)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
struct clk_init_data init;
const char *clk_parents[1];
- init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
- dev_name(indio_dev->dev.parent));
+ init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));
if (!init.name)
return -ENOMEM;
priv->clk_div.hw.init = &init;
priv->clk_div.flags = 0;
- priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
- &priv->clk_div.hw);
+ priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);
if (WARN_ON(IS_ERR(priv->adc_div_clk)))
return PTR_ERR(priv->adc_div_clk);
- init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
- dev_name(indio_dev->dev.parent));
+ init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));
if (!init.name)
return -ENOMEM;
priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
priv->clk_gate.hw.init = &init;
- priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
if (WARN_ON(IS_ERR(priv->adc_clk)))
return PTR_ERR(priv->adc_clk);
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
+ struct device *dev = indio_dev->dev.parent;
struct nvmem_cell *temperature_calib;
size_t read_len;
int ret;
- temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent,
- "temperature_calib");
+ temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib");
if (IS_ERR(temperature_calib)) {
ret = PTR_ERR(temperature_calib);
if (ret == -ENODEV)
return 0;
- return dev_err_probe(indio_dev->dev.parent, ret,
- "failed to get temperature_calib cell\n");
+ return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");
}
- priv->tsc_regmap =
- syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node,
- "amlogic,hhi-sysctrl");
- if (IS_ERR(priv->tsc_regmap)) {
- dev_err(indio_dev->dev.parent,
- "failed to get amlogic,hhi-sysctrl regmap\n");
- return PTR_ERR(priv->tsc_regmap);
- }
+ priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
+ if (IS_ERR(priv->tsc_regmap))
+ return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
+ "failed to get amlogic,hhi-sysctrl regmap\n");
read_len = MESON_SAR_ADC_EFUSE_BYTES;
buf = nvmem_cell_read(temperature_calib, &read_len);
- if (IS_ERR(buf)) {
- dev_err(indio_dev->dev.parent,
- "failed to read temperature_calib cell\n");
- return PTR_ERR(buf);
- } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
+ if (IS_ERR(buf))
+ return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");
+ if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
kfree(buf);
- dev_err(indio_dev->dev.parent,
- "invalid read size of temperature_calib cell\n");
- return -EINVAL;
+ return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");
}
trimming_bits = priv->param->temperature_trimming_bits;
static int meson_sar_adc_init(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
int regval, i, ret;
/*
}
ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
- if (ret) {
- dev_err(indio_dev->dev.parent,
- "failed to set adc parent to clkin\n");
- return ret;
- }
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
- if (ret) {
- dev_err(indio_dev->dev.parent,
- "failed to set adc clock rate\n");
- return ret;
- }
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to set adc clock rate\n");
return 0;
}
static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct device *dev = indio_dev->dev.parent;
int ret;
u32 regval;
ret = regulator_enable(priv->vref);
if (ret < 0) {
- dev_err(indio_dev->dev.parent,
- "failed to enable vref regulator\n");
+ dev_err(dev, "failed to enable vref regulator\n");
goto err_vref;
}
ret = clk_prepare_enable(priv->core_clk);
if (ret) {
- dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ dev_err(dev, "failed to enable core clk\n");
goto err_core_clk;
}
ret = clk_prepare_enable(priv->adc_clk);
if (ret) {
- dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ dev_err(dev, "failed to enable adc clk\n");
goto err_adc_clk;
}
{
const struct meson_sar_adc_data *match_data;
struct meson_sar_adc_priv *priv;
+ struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
void __iomem *base;
int irq, ret;
- indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
- if (!indio_dev) {
- dev_err(&pdev->dev, "failed allocating iio device\n");
- return -ENOMEM;
- }
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
+ if (!indio_dev)
+ return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n");
priv = iio_priv(indio_dev);
init_completion(&priv->done);
- match_data = of_device_get_match_data(&pdev->dev);
- if (!match_data) {
- dev_err(&pdev->dev, "failed to get match data\n");
- return -ENODEV;
- }
+ match_data = of_device_get_match_data(dev);
+ if (!match_data)
+ return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
priv->param = match_data->param;
if (IS_ERR(base))
return PTR_ERR(base);
- priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
- priv->param->regmap_config);
+ priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
- irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+ irq = irq_of_parse_and_map(dev->of_node, 0);
if (!irq)
return -EINVAL;
- ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
- dev_name(&pdev->dev), indio_dev);
+ ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);
if (ret)
return ret;
- priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ priv->clkin = devm_clk_get(dev, "clkin");
if (IS_ERR(priv->clkin))
- return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkin),
- "failed to get clkin\n");
+ return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
- priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ priv->core_clk = devm_clk_get(dev, "core");
if (IS_ERR(priv->core_clk))
- return dev_err_probe(&pdev->dev, PTR_ERR(priv->core_clk),
- "failed to get core clk\n");
+ return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
- priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
- if (IS_ERR(priv->adc_clk)) {
- if (PTR_ERR(priv->adc_clk) == -ENOENT)
- priv->adc_clk = NULL;
- else
- return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_clk),
- "failed to get adc clk\n");
- }
+ priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk))
+ return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");
- priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
- if (IS_ERR(priv->adc_sel_clk)) {
- if (PTR_ERR(priv->adc_sel_clk) == -ENOENT)
- priv->adc_sel_clk = NULL;
- else
- return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_sel_clk),
- "failed to get adc_sel clk\n");
- }
+ priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk))
+ return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");
/* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
if (!priv->adc_clk) {
return ret;
}
- priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ priv->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(priv->vref))
- return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
- "failed to get vref regulator\n");
+ return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");
priv->calibscale = MILLION;
ret = meson_sar_adc_calib(indio_dev);
if (ret)
- dev_warn(&pdev->dev, "calibration failed\n");
+ dev_warn(dev, "calibration failed\n");
platform_set_drvdata(pdev, indio_dev);
return meson_sar_adc_hw_disable(indio_dev);
}
-static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
+static int meson_sar_adc_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
return meson_sar_adc_hw_disable(indio_dev);
}
-static int __maybe_unused meson_sar_adc_resume(struct device *dev)
+static int meson_sar_adc_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
return meson_sar_adc_hw_enable(indio_dev);
}
-static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
- meson_sar_adc_suspend, meson_sar_adc_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
+ meson_sar_adc_suspend, meson_sar_adc_resume);
static struct platform_driver meson_sar_adc_driver = {
.probe = meson_sar_adc_probe,
.driver = {
.name = "meson-saradc",
.of_match_table = meson_sar_adc_of_match,
- .pm = &meson_sar_adc_pm_ops,
+ .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),
},
};
projects / linux-2.6-microblaze.git / blobdiff