Merge tag 'for-linus-20190524' of git://git.kernel.dk/linux-block

[linux-2.6-microblaze.git] / drivers / gpu / drm / sun4i / sun8i_hdmi_phy.c

diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 66ea3a9..43643ad 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
                                 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
                                 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
                ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
-                                SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);
+                                SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
+                                SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
        }
 
        regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
@@ -672,22 +673,13 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
                                goto err_put_clk_pll0;
                        }
                }
-
-               ret = sun8i_phy_clk_create(phy, dev,
-                                          phy->variant->has_second_pll);
-               if (ret) {
-                       dev_err(dev, "Couldn't create the PHY clock\n");
-                       goto err_put_clk_pll1;
-               }
-
-               clk_prepare_enable(phy->clk_phy);
        }
 
        phy->rst_phy = of_reset_control_get_shared(node, "phy");
        if (IS_ERR(phy->rst_phy)) {
                dev_err(dev, "Could not get phy reset control\n");
                ret = PTR_ERR(phy->rst_phy);
-               goto err_disable_clk_phy;
+               goto err_put_clk_pll1;
        }
 
        ret = reset_control_deassert(phy->rst_phy);
@@ -708,18 +700,29 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
                goto err_disable_clk_bus;
        }
 
+       if (phy->variant->has_phy_clk) {
+               ret = sun8i_phy_clk_create(phy, dev,
+                                          phy->variant->has_second_pll);
+               if (ret) {
+                       dev_err(dev, "Couldn't create the PHY clock\n");
+                       goto err_disable_clk_mod;
+               }
+
+               clk_prepare_enable(phy->clk_phy);
+       }
+
        hdmi->phy = phy;
 
        return 0;
 
+err_disable_clk_mod:
+       clk_disable_unprepare(phy->clk_mod);
 err_disable_clk_bus:
        clk_disable_unprepare(phy->clk_bus);
 err_deassert_rst_phy:
        reset_control_assert(phy->rst_phy);
 err_put_rst_phy:
        reset_control_put(phy->rst_phy);
-err_disable_clk_phy:
-       clk_disable_unprepare(phy->clk_phy);
 err_put_clk_pll1:
        clk_put(phy->clk_pll1);
 err_put_clk_pll0: