drm/radeon: add large PTE support for NI, SI and CIK v5
[linux-2.6-microblaze.git] / drivers / gpu / drm / radeon / ni.c
index bf6300c..5e8db9b 100644 (file)
@@ -1228,12 +1228,14 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
               SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
        /* Setup L2 cache */
        WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
+              ENABLE_L2_FRAGMENT_PROCESSING |
               ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
               ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
               EFFECTIVE_L2_QUEUE_SIZE(7) |
               CONTEXT1_IDENTITY_ACCESS_MODE(1));
        WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
        WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
+              BANK_SELECT(6) |
               L2_CACHE_BIGK_FRAGMENT_SIZE(6));
        /* setup context0 */
        WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
@@ -1642,8 +1644,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                ring = &rdev->ring[ridx[i]];
                WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
 
-               ring->rptr = ring->wptr = 0;
-               WREG32(cp_rb_rptr[i], ring->rptr);
+               ring->wptr = 0;
+               WREG32(cp_rb_rptr[i], 0);
                WREG32(cp_rb_wptr[i], ring->wptr);
 
                mdelay(1);
@@ -1917,11 +1919,9 @@ bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
        if (!(reset_mask & (RADEON_RESET_GFX |
                            RADEON_RESET_COMPUTE |
                            RADEON_RESET_CP))) {
-               radeon_ring_lockup_update(ring);
+               radeon_ring_lockup_update(rdev, ring);
                return false;
        }
-       /* force CP activities */
-       radeon_ring_force_activity(rdev, ring);
        return radeon_ring_test_lockup(rdev, ring);
 }