Merge tag 'f2fs-for-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jaegeu...

[linux-2.6-microblaze.git] / drivers / gpu / drm / msm / adreno / a6xx_gmu.c

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 3d55e15..b349692 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -512,19 +512,26 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
        struct platform_device *pdev = to_platform_device(gmu->dev);
        void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
-       void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
+       void __iomem *seqptr;
        uint32_t pdc_address_offset;
+       bool pdc_in_aop = false;
 
-       if (!pdcptr || !seqptr)
+       if (!pdcptr)
                goto err;
 
-       if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
+       if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
+               pdc_in_aop = true;
+       else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
                pdc_address_offset = 0x30090;
-       else if (adreno_is_a650(adreno_gpu))
-               pdc_address_offset = 0x300a0;
        else
                pdc_address_offset = 0x30080;
 
+       if (!pdc_in_aop) {
+               seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
+               if (!seqptr)
+                       goto err;
+       }
+
        /* Disable SDE clock gating */
        gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
 
@@ -542,7 +549,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
        gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
 
        /* Load RSC sequencer uCode for sleep and wakeup */
-       if (adreno_is_a650(adreno_gpu)) {
+       if (adreno_is_a650_family(adreno_gpu)) {
                gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
                gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
                gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
@@ -556,6 +563,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
                gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
        }
 
+       if (pdc_in_aop)
+               goto setup_pdc;
+
        /* Load PDC sequencer uCode for power up and power down sequence */
        pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
        pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
@@ -587,7 +597,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
 
        pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
        pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
-       if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
+       if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
                pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
        else
                pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
@@ -596,6 +606,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
        pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
 
        /* Setup GPU PDC */
+setup_pdc:
        pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
        pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
 
@@ -687,7 +698,7 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
        u32 itcm_base = 0x00000000;
        u32 dtcm_base = 0x00040000;
 
-       if (adreno_is_a650(adreno_gpu))
+       if (adreno_is_a650_family(adreno_gpu))
                dtcm_base = 0x10004000;
 
        if (gmu->legacy) {
@@ -740,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
        int ret;
        u32 chipid;
 
-       if (adreno_is_a650(adreno_gpu))
+       if (adreno_is_a650_family(adreno_gpu)) {
+               gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
                gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
+       }
 
        if (state == GMU_WARM_BOOT) {
                ret = a6xx_rpmh_start(gmu);
@@ -1346,7 +1359,7 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
         * The GMU handles its own frequency switching so build a list of
         * available frequencies to send during initialization
         */
-       ret = dev_pm_opp_of_add_table(gmu->dev);
+       ret = devm_pm_opp_of_add_table(gmu->dev);
        if (ret) {
                DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
                return ret;
@@ -1483,12 +1496,28 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
        if (ret)
                goto err_put_device;
 
+
+       /* A660 now requires handling "prealloc requests" in GMU firmware
+        * For now just hardcode allocations based on the known firmware.
+        * note: there is no indication that these correspond to "dummy" or
+        * "debug" regions, but this "guess" allows reusing these BOs which
+        * are otherwise unused by a660.
+        */
+       gmu->dummy.size = SZ_4K;
+       if (adreno_is_a660(adreno_gpu)) {
+               ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
+               if (ret)
+                       goto err_memory;
+
+               gmu->dummy.size = SZ_8K;
+       }
+
        /* Allocate memory for the GMU dummy page */
-       ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
+       ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
        if (ret)
                goto err_memory;
 
-       if (adreno_is_a650(adreno_gpu)) {
+       if (adreno_is_a650_family(adreno_gpu)) {
                ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
                        SZ_16M - SZ_16K, 0x04000);
                if (ret)
@@ -1530,7 +1559,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
                goto err_memory;
        }
 
-       if (adreno_is_a650(adreno_gpu)) {
+       if (adreno_is_a650_family(adreno_gpu)) {
                gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
                if (IS_ERR(gmu->rscc))
                        goto err_mmio;