}
struct a6xx_gmu_oob_bits {
- int set, ack, set_new, ack_new;
+ int set, ack, set_new, ack_new, clear, clear_new;
const char *name;
};
.ack = 24,
.set_new = 30,
.ack_new = 31,
+ .clear = 24,
+ .clear_new = 31,
},
[GMU_OOB_PERFCOUNTER_SET] = {
.ack = 25,
.set_new = 28,
.ack_new = 30,
+ .clear = 25,
+ .clear_new = 29,
},
[GMU_OOB_BOOT_SLUMBER] = {
.name = "BOOT_SLUMBER",
.set = 22,
.ack = 30,
+ .clear = 30,
},
[GMU_OOB_DCVS_SET] = {
.name = "GPU_DCVS",
.set = 23,
.ack = 31,
+ .clear = 31,
},
};
return;
if (gmu->legacy)
- bit = a6xx_gmu_oob_bits[state].ack;
+ bit = a6xx_gmu_oob_bits[state].clear;
else
- bit = a6xx_gmu_oob_bits[state].ack_new;
+ bit = a6xx_gmu_oob_bits[state].clear_new;
gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
}