drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT
[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / intel_uncore.c
index 8d5a933..ede3a53 100644 (file)
@@ -1051,37 +1051,37 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
-       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 };
 
@@ -1089,33 +1089,33 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
        GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8800, 0x8bff, 0),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
        GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
        GEN_FW_RANGE(0x9560, 0x95ff, 0),
-       GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24000, 0x2407f, 0),
-       GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x40000, 0x1bffff, 0),
        GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
        GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
@@ -1126,39 +1126,39 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
-       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
-       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x40000, 0x1bffff, 0),
        GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
        GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
        GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
-       GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
        GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
        GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
@@ -1469,7 +1469,7 @@ static int __fw_domain_init(struct intel_uncore *uncore,
        d->id = domain_id;
 
        BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
-       BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
+       BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
        BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
        BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
        BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
@@ -1538,9 +1538,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
                fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
                               FORCEWAKE_RENDER_GEN9,
                               FORCEWAKE_ACK_RENDER_GEN9);
-               fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
-                              FORCEWAKE_BLITTER_GEN9,
-                              FORCEWAKE_ACK_BLITTER_GEN9);
+               fw_domain_init(uncore, FW_DOMAIN_ID_GT,
+                              FORCEWAKE_GT_GEN9,
+                              FORCEWAKE_ACK_GT_GEN9);
 
                for (i = 0; i < I915_MAX_VCS; i++) {
                        if (!__HAS_ENGINE(emask, _VCS(i)))
@@ -1564,9 +1564,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
                fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
                               FORCEWAKE_RENDER_GEN9,
                               FORCEWAKE_ACK_RENDER_GEN9);
-               fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
-                              FORCEWAKE_BLITTER_GEN9,
-                              FORCEWAKE_ACK_BLITTER_GEN9);
+               fw_domain_init(uncore, FW_DOMAIN_ID_GT,
+                              FORCEWAKE_GT_GEN9,
+                              FORCEWAKE_ACK_GT_GEN9);
                fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
                               FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
        } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
@@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
         * clobbering the GTT which we want ioremap_wc instead. Fortunately,
         * the register BAR remains the same size for all the earlier
         * generations up to Ironlake.
+        * For dgfx chips register range is expanded to 4MB.
         */
        if (INTEL_GEN(i915) < 5)
                mmio_size = 512 * 1024;
+       else if (IS_DGFX(i915))
+               mmio_size = 4 * 1024 * 1024;
        else
                mmio_size = 2 * 1024 * 1024;
+
        uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
        if (uncore->regs == NULL) {
                drm_err(&i915->drm, "failed to map registers\n");
@@ -1993,13 +1997,14 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
                                 unsigned int slow_timeout_ms,
                                 u32 *out_value)
 {
-       u32 reg_value;
+       u32 reg_value = 0;
 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
        int ret;
 
        /* Catch any overuse of this function */
        might_sleep_if(slow_timeout_ms);
        GEM_BUG_ON(fast_timeout_us > 20000);
+       GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
 
        ret = -ETIMEDOUT;
        if (fast_timeout_us && fast_timeout_us <= 20000)