drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfabbe0..f54375b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -100,12 +100,6 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
         */
        I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
                   DISP_FBC_MEMORY_WAKE);
-
-       if (IS_SKYLAKE(dev_priv)) {
-               /* WaDisableDopClockGating */
-               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
-                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-       }
 }
 
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -3579,11 +3573,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
        _ilk_disable_lp_wm(dev_priv, dirty);
 
        if (dirty & WM_DIRTY_PIPE(PIPE_A))
-               I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
+               I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
        if (dirty & WM_DIRTY_PIPE(PIPE_B))
-               I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
+               I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
        if (dirty & WM_DIRTY_PIPE(PIPE_C))
-               I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
+               I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
 
        if (dirty & WM_DIRTY_DDB) {
                if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3712,7 +3706,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
  *  - All planes can enable watermarks for latencies >= SAGV engine block time
  *  - We're not using an interlaced display configuration
  */
-int
+static int
 intel_enable_sagv(struct drm_i915_private *dev_priv)
 {
        int ret;
@@ -3746,7 +3740,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
        return 0;
 }
 
-int
+static int
 intel_disable_sagv(struct drm_i915_private *dev_priv)
 {
        int ret;
@@ -6293,13 +6287,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
        struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
        struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
        enum pipe pipe = crtc->pipe;
-       static const i915_reg_t wm0_pipe_reg[] = {
-               [PIPE_A] = WM0_PIPEA_ILK,
-               [PIPE_B] = WM0_PIPEB_ILK,
-               [PIPE_C] = WM0_PIPEC_IVB,
-       };
 
-       hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
+       hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
 
        memset(active, 0, sizeof(*active));
 
@@ -7122,27 +7111,28 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
                         0, CNL_DELAY_PMRSP);
 }
 
-static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen12_init_clock_gating(struct drm_i915_private *i915)
 {
-       u32 vd_pg_enable = 0;
        unsigned int i;
 
+       /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
+       for (i = 0; i < I915_MAX_VCS; i++)
+               if (HAS_ENGINE(&i915->gt, _VCS(i)))
+                       intel_uncore_rmw(&i915->uncore, POWERGATE_ENABLE, 0,
+                                        VDN_HCP_POWERGATE_ENABLE(i) |
+                                        VDN_MFX_POWERGATE_ENABLE(i));
+}
+
+static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+       gen12_init_clock_gating(dev_priv);
+
        /* Wa_1409120013:tgl */
        I915_WRITE(ILK_DPFC_CHICKEN,
                   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
-       /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
-       for (i = 0; i < I915_MAX_VCS; i++) {
-               if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
-                       vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
-                                       VDN_MFX_POWERGATE_ENABLE(i);
-       }
-
-       I915_WRITE(POWERGATE_ENABLE,
-                  I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
-
        /* Wa_1409825376:tgl (pre-prod)*/
-       if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+       if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
                I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
                           TGL_VRH_GATING_DIS);
 
@@ -7151,6 +7141,16 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
                         0, DFR_DISABLE);
 }
 
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+       gen12_init_clock_gating(dev_priv);
+
+       /* Wa_1409836686:dg1[a0] */
+       if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+               I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+                          DPT_GATING_DIS);
+}
+
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        if (!HAS_PCH_CNP(dev_priv))
@@ -7203,6 +7203,10 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
        cnp_init_clock_gating(dev_priv);
        gen9_init_clock_gating(dev_priv);
 
+       /* WAC6entrylatency:cfl */
+       I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+                  FBC_LLC_FULLY_OPEN);
+
        /*
         * WaFbcTurnOffFbcWatermark:cfl
         * Display WA #0562: cfl
@@ -7222,13 +7226,17 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        gen9_init_clock_gating(dev_priv);
 
+       /* WAC6entrylatency:kbl */
+       I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+                  FBC_LLC_FULLY_OPEN);
+
        /* WaDisableSDEUnitClockGating:kbl */
-       if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+       if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
        /* WaDisableGamClockGating:kbl */
-       if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+       if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
                I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
                           GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
@@ -7251,6 +7259,10 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        gen9_init_clock_gating(dev_priv);
 
+       /* WaDisableDopClockGating:skl */
+       I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
+                  ~GEN7_DOP_CLOCK_GATE_ENABLE);
+
        /* WAC6entrylatency:skl */
        I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
                   FBC_LLC_FULLY_OPEN);
@@ -7592,7 +7604,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-       if (IS_GEN(dev_priv, 12))
+       if (IS_DG1(dev_priv))
+               dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+       else if (IS_GEN(dev_priv, 12))
                dev_priv->display.init_clock_gating = tgl_init_clock_gating;
        else if (IS_GEN(dev_priv, 11))
                dev_priv->display.init_clock_gating = icl_init_clock_gating;