drm/i915/ehl: Add ElkhartLake platform

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / intel_device_info.h

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e8b8661..98acefa 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -73,14 +73,14 @@ enum intel_platform {
        INTEL_CANNONLAKE,
        /* gen11 */
        INTEL_ICELAKE,
+       INTEL_ELKHARTLAKE,
        INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
+enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
        INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-       INTEL_PPGTT_FULL_4LVL,
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
@@ -150,19 +150,21 @@ struct sseu_dev_info {
        u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
 };
 
-typedef u8 intel_ring_mask_t;
+typedef u8 intel_engine_mask_t;
 
 struct intel_device_info {
        u16 gen_mask;
 
        u8 gen;
        u8 gt; /* GT number, 0 if undefined */
-       intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+       intel_engine_mask_t engine_mask; /* Engines supported by the HW */
 
        enum intel_platform platform;
        u32 platform_mask;
 
-       enum intel_ppgtt ppgtt;
+       enum intel_ppgtt_type ppgtt_type;
+       unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
+
        unsigned int page_sizes; /* page sizes supported by the HW */
 
        u32 display_mmio_offset;
@@ -200,7 +202,7 @@ struct intel_runtime_info {
        u8 num_sprites[I915_MAX_PIPES];
        u8 num_scalers[I915_MAX_PIPES];
 
-       u8 num_rings;
+       u8 num_engines;
 
        /* Slice/subslice/EU info */
        struct sseu_dev_info sseu;