Merge tag 'csky-for-linus-5.14-rc1' of git://github.com/c-sky/csky-linux

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / intel_device_info.c

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index de02207..7eaa92f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -67,6 +67,7 @@ static const char * const platform_names[] = {
        PLATFORM_NAME(ROCKETLAKE),
        PLATFORM_NAME(DG1),
        PLATFORM_NAME(ALDERLAKE_S),
+       PLATFORM_NAME(ALDERLAKE_P),
 };
 #undef PLATFORM_NAME
 
@@ -95,7 +96,9 @@ static const char *iommu_name(void)
 void intel_device_info_print_static(const struct intel_device_info *info,
                                    struct drm_printer *p)
 {
-       drm_printf(p, "gen: %d\n", info->gen);
+       drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
+       drm_printf(p, "media_ver: %u\n", info->media_ver);
+       drm_printf(p, "display_ver: %u\n", info->display.ver);
        drm_printf(p, "gt: %d\n", info->gt);
        drm_printf(p, "iommu: %s\n", iommu_name());
        drm_printf(p, "memory-regions: %x\n", info->memory_regions);
@@ -254,10 +257,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
        if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
                for_each_pipe(dev_priv, pipe)
                        runtime->num_scalers[pipe] = 0;
-       else if (INTEL_GEN(dev_priv) >= 10) {
+       else if (GRAPHICS_VER(dev_priv) >= 10) {
                for_each_pipe(dev_priv, pipe)
                        runtime->num_scalers[pipe] = 2;
-       } else if (IS_GEN(dev_priv, 9)) {
+       } else if (GRAPHICS_VER(dev_priv) == 9) {
                runtime->num_scalers[PIPE_A] = 2;
                runtime->num_scalers[PIPE_B] = 2;
                runtime->num_scalers[PIPE_C] = 1;
@@ -265,13 +268,13 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
        BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-       if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+       if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
                for_each_pipe(dev_priv, pipe)
                        runtime->num_sprites[pipe] = 4;
-       else if (INTEL_GEN(dev_priv) >= 11)
+       else if (GRAPHICS_VER(dev_priv) >= 11)
                for_each_pipe(dev_priv, pipe)
                        runtime->num_sprites[pipe] = 6;
-       else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
+       else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
                for_each_pipe(dev_priv, pipe)
                        runtime->num_sprites[pipe] = 3;
        else if (IS_BROXTON(dev_priv)) {
@@ -290,12 +293,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
        } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                for_each_pipe(dev_priv, pipe)
                        runtime->num_sprites[pipe] = 2;
-       } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+       } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
                for_each_pipe(dev_priv, pipe)
                        runtime->num_sprites[pipe] = 1;
        }
 
-       if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
+       if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
            HAS_PCH_SPLIT(dev_priv)) {
                u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
                u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
@@ -322,7 +325,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                        info->pipe_mask &= ~BIT(PIPE_C);
                        info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
                }
-       } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
+       } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
                u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 
                if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
@@ -337,7 +340,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                        info->pipe_mask &= ~BIT(PIPE_C);
                        info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
                }
-               if (INTEL_GEN(dev_priv) >= 12 &&
+               if (GRAPHICS_VER(dev_priv) >= 12 &&
                    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
                        info->pipe_mask &= ~BIT(PIPE_D);
                        info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
@@ -349,15 +352,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
                        info->display.has_fbc = 0;
 
-               if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
-                       info->display.has_csr = 0;
+               if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
+                       info->display.has_dmc = 0;
 
-               if (INTEL_GEN(dev_priv) >= 10 &&
+               if (GRAPHICS_VER(dev_priv) >= 10 &&
                    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
                        info->display.has_dsc = 0;
        }
 
-       if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
+       if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
                drm_info(&dev_priv->drm,
                         "Disabling ppGTT for VT-d support\n");
                info->ppgtt_type = INTEL_PPGTT_NONE;