Merge tag 'drm-intel-gt-next-2021-05-28' of git://anongit.freedesktop.org/drm/drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07cca3b..c294e3f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -416,6 +416,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN11_VECS_SFC_USAGE(engine)           _MMIO((engine)->mmio_base + 0x2014)
 #define   GEN11_VECS_SFC_USAGE_BIT             (1 << 0)
 
+#define GEN12_HCP_SFC_FORCED_LOCK(engine)      _MMIO((engine)->mmio_base + 0x2910)
+#define   GEN12_HCP_SFC_FORCED_LOCK_BIT                REG_BIT(0)
+#define GEN12_HCP_SFC_LOCK_STATUS(engine)      _MMIO((engine)->mmio_base + 0x2914)
+#define   GEN12_HCP_SFC_LOCK_ACK_BIT           REG_BIT(1)
+#define   GEN12_HCP_SFC_USAGE_BIT                      REG_BIT(0)
+
 #define GEN12_SFC_DONE(n)              _MMIO(0x1cc00 + (n) * 0x100)
 #define GEN12_SFC_DONE_MAX             4
 
@@ -487,6 +493,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GAB_CTL                                _MMIO(0x24000)
 #define   GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
 
+#define GU_CNTL                                _MMIO(0x101010)
+#define   LMEM_INIT                    REG_BIT(7)
+
 #define GEN6_STOLEN_RESERVED           _MMIO(0x1082C0)
 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
@@ -2715,6 +2724,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
 #define RING_CTX_TIMESTAMP(base)       _MMIO((base) + 0x3a8) /* gen8+ */
 
+#define VDBOX_CGCTL3F10(base)          _MMIO((base) + 0x3f10)
+#define   IECPUNIT_CLKGATE_DIS         REG_BIT(22)
+
 #define ERROR_GEN6     _MMIO(0x40a0)
 #define GEN7_ERR_INT   _MMIO(0x44040)
 #define   ERR_INT_POISON               (1 << 31)
@@ -3781,8 +3793,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define CSHRDDR3CTL_DDR3       (1 << 2)
 
 /* 965 MCH register controlling DRAM channel configuration */
-#define C0DRB3                 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
-#define C1DRB3                 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
+#define C0DRB3_BW              _MMIO(MCHBAR_MIRROR_BASE + 0x206)
+#define C1DRB3_BW              _MMIO(MCHBAR_MIRROR_BASE + 0x606)
 
 /* snb MCH registers for reading the DRAM channel configuration */
 #define MAD_DIMM_C0                    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
@@ -12208,6 +12220,7 @@ enum skl_power_gate {
 #define GEN12_GLOBAL_MOCS(i)   _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
 
 #define GEN12_GSMBASE                  _MMIO(0x108100)
+#define GEN12_DSMBASE                  _MMIO(0x1080C0)
 
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)