Merge drm/drm-next into drm-intel-next-queued

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d6483b5..5898f59 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1793,8 +1793,10 @@ enum i915_power_well_id {
  */
 #define _ICL_COMBOPHY_A                        0x162000
 #define _ICL_COMBOPHY_B                        0x6C000
+#define _EHL_COMBOPHY_C                        0x160000
 #define _ICL_COMBOPHY(port)            _PICK(port, _ICL_COMBOPHY_A, \
-                                             _ICL_COMBOPHY_B)
+                                             _ICL_COMBOPHY_B, \
+                                             _EHL_COMBOPHY_C)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, port)      (_ICL_COMBOPHY(port) + \
@@ -1896,6 +1898,8 @@ enum i915_power_well_id {
 #define ICL_PORT_PCS_DW1_GRP(port)     _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
 #define ICL_PORT_PCS_DW1_LN0(port)     _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
 #define   COMMON_KEEPER_EN             (1 << 26)
+#define   LATENCY_OPTIM_MASK           (0x3 << 2)
+#define   LATENCY_OPTIM_VAL(x)         ((x) << 2)
 
 /* CNL/ICL Port TX registers */
 #define _CNL_PORT_TX_AE_GRP_OFFSET             0x162340
@@ -1991,6 +1995,10 @@ enum i915_power_well_id {
 #define   N_SCALAR(x)                  ((x) << 24)
 #define   N_SCALAR_MASK                        (0x7F << 24)
 
+#define _ICL_DPHY_CHKN_REG                     0x194
+#define ICL_DPHY_CHKN(port)                    _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
+#define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP     REG_BIT(7)
+
 #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
        _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
 
@@ -6284,6 +6292,7 @@ enum {
 #define _DSPATILEOFF                           0x701A4 /* 965+ only */
 #define _DSPAOFFSET                            0x701A4 /* HSW */
 #define _DSPASURFLIVE                          0x701AC
+#define _DSPAGAMC                              0x701E0
 
 #define DSPCNTR(plane)         _MMIO_PIPE2(plane, _DSPACNTR)
 #define DSPADDR(plane)         _MMIO_PIPE2(plane, _DSPAADDR)
@@ -6295,6 +6304,7 @@ enum {
 #define DSPLINOFF(plane)       DSPADDR(plane)
 #define DSPOFFSET(plane)       _MMIO_PIPE2(plane, _DSPAOFFSET)
 #define DSPSURFLIVE(plane)     _MMIO_PIPE2(plane, _DSPASURFLIVE)
+#define DSPGAMC(plane, i)      _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
 
 /* CHV pipe B blender and primary plane */
 #define _CHV_BLEND_A           0x60a00
@@ -6397,6 +6407,7 @@ enum {
 #define _DVSAKEYMAXVAL         0x721a0
 #define _DVSATILEOFF           0x721a4
 #define _DVSASURFLIVE          0x721ac
+#define _DVSAGAMC_G4X          0x721e0 /* g4x */
 #define _DVSASCALE             0x72204
 #define   DVS_SCALE_ENABLE     (1 << 31)
 #define   DVS_FILTER_MASK      (3 << 29)
@@ -6405,7 +6416,8 @@ enum {
 #define   DVS_FILTER_SOFTENING (2 << 29)
 #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
 #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
-#define _DVSAGAMC              0x72300
+#define _DVSAGAMC_ILK          0x72300 /* ilk/snb */
+#define _DVSAGAMCMAX_ILK       0x72340 /* ilk/snb */
 
 #define _DVSBCNTR              0x73180
 #define _DVSBLINOFF            0x73184
@@ -6418,8 +6430,10 @@ enum {
 #define _DVSBKEYMAXVAL         0x731a0
 #define _DVSBTILEOFF           0x731a4
 #define _DVSBSURFLIVE          0x731ac
+#define _DVSBGAMC_G4X          0x731e0 /* g4x */
 #define _DVSBSCALE             0x73204
-#define _DVSBGAMC              0x73300
+#define _DVSBGAMC_ILK          0x73300 /* ilk/snb */
+#define _DVSBGAMCMAX_ILK       0x73340 /* ilk/snb */
 
 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
@@ -6433,6 +6447,9 @@ enum {
 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
+#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
+#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
 
 #define _SPRA_CTL              0x70280
 #define   SPRITE_ENABLE                        (1 << 31)
@@ -6457,7 +6474,7 @@ enum {
 #define   SPRITE_YUV_ORDER_VYUY                (3 << 16)
 #define   SPRITE_ROTATE_180            (1 << 15)
 #define   SPRITE_TRICKLE_FEED_DISABLE  (1 << 14)
-#define   SPRITE_INT_GAMMA_ENABLE      (1 << 13)
+#define   SPRITE_INT_GAMMA_DISABLE     (1 << 13)
 #define   SPRITE_TILED                 (1 << 10)
 #define   SPRITE_DEST_KEY              (1 << 2)
 #define _SPRA_LINOFF           0x70284
@@ -6480,6 +6497,8 @@ enum {
 #define   SPRITE_VERTICAL_OFFSET_HALF  (1 << 28) /* must be enabled below */
 #define   SPRITE_VERTICAL_OFFSET_ENABLE        (1 << 27)
 #define _SPRA_GAMC             0x70400
+#define _SPRA_GAMC16           0x70440
+#define _SPRA_GAMC17           0x7044c
 
 #define _SPRB_CTL              0x71280
 #define _SPRB_LINOFF           0x71284
@@ -6495,6 +6514,8 @@ enum {
 #define _SPRB_SURFLIVE         0x712ac
 #define _SPRB_SCALE            0x71304
 #define _SPRB_GAMC             0x71400
+#define _SPRB_GAMC16           0x71440
+#define _SPRB_GAMC17           0x7144c
 
 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
@@ -6508,7 +6529,9 @@ enum {
 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
-#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
+#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
+#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
+#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
 
 #define _SPACNTR               (VLV_DISPLAY_BASE + 0x72180)
@@ -6551,7 +6574,7 @@ enum {
 #define _SPACLRC1              (VLV_DISPLAY_BASE + 0x721d4)
 #define   SP_SH_SIN(x)                 (((x) & 0x7ff) << 16) /* s4.7 */
 #define   SP_SH_COS(x)                 (x) /* u3.7 */
-#define _SPAGAMC               (VLV_DISPLAY_BASE + 0x721f4)
+#define _SPAGAMC               (VLV_DISPLAY_BASE + 0x721e0)
 
 #define _SPBCNTR               (VLV_DISPLAY_BASE + 0x72280)
 #define _SPBLINOFF             (VLV_DISPLAY_BASE + 0x72284)
@@ -6566,10 +6589,12 @@ enum {
 #define _SPBCONSTALPHA         (VLV_DISPLAY_BASE + 0x722a8)
 #define _SPBCLRC0              (VLV_DISPLAY_BASE + 0x722d0)
 #define _SPBCLRC1              (VLV_DISPLAY_BASE + 0x722d4)
-#define _SPBGAMC               (VLV_DISPLAY_BASE + 0x722f4)
+#define _SPBGAMC               (VLV_DISPLAY_BASE + 0x722e0)
 
+#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+       _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
-       _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
+       _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
 
 #define SPCNTR(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
 #define SPLINOFF(pipe, plane_id)       _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
@@ -6584,7 +6609,7 @@ enum {
 #define SPCONSTALPHA(pipe, plane_id)   _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
 #define SPCLRC0(pipe, plane_id)                _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
 #define SPCLRC1(pipe, plane_id)                _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
-#define SPGAMC(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
+#define SPGAMC(pipe, plane_id, i)      _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
 
 /*
  * CHV pipe B sprite CSC
@@ -11145,6 +11170,7 @@ enum skl_power_gate {
 #define _ICL_PHY_MISC_B                0x64C04
 #define ICL_PHY_MISC(port)     _MMIO_PORT(port, _ICL_PHY_MISC_A, \
                                                 _ICL_PHY_MISC_B)
+#define  ICL_PHY_MISC_MUX_DDID                 (1 << 28)
 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN      (1 << 23)
 
 /* Icelake Display Stream Compression Registers */