drm/i915/ehl: Set proper eu slice/subslice parameters for EHL

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_pci.c

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3cf697e..a7e1611 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -349,7 +349,8 @@ static const struct intel_device_info intel_ironlake_m_info = {
        .has_llc = 1, \
        .has_rc6 = 1, \
        .has_rc6p = 1, \
-       .ppgtt = INTEL_PPGTT_ALIASING, \
+       .ppgtt_type = INTEL_PPGTT_ALIASING, \
+       .ppgtt_size = 31, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        GEN_DEFAULT_PAGE_SIZES
@@ -394,7 +395,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
        .has_llc = 1, \
        .has_rc6 = 1, \
        .has_rc6p = 1, \
-       .ppgtt = INTEL_PPGTT_FULL, \
+       .ppgtt_type = INTEL_PPGTT_FULL, \
+       .ppgtt_size = 31, \
        IVB_PIPE_OFFSETS, \
        IVB_CURSOR_OFFSETS, \
        GEN_DEFAULT_PAGE_SIZES
@@ -447,7 +449,8 @@ static const struct intel_device_info intel_valleyview_info = {
        .has_rc6 = 1,
        .display.has_gmch = 1,
        .display.has_hotplug = 1,
-       .ppgtt = INTEL_PPGTT_FULL,
+       .ppgtt_type = INTEL_PPGTT_FULL,
+       .ppgtt_size = 31,
        .has_snoop = true,
        .has_coherent_ggtt = false,
        .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
@@ -495,7 +498,8 @@ static const struct intel_device_info intel_haswell_gt3_info = {
        .page_sizes = I915_GTT_PAGE_SIZE_4K | \
                      I915_GTT_PAGE_SIZE_2M, \
        .has_logical_ring_contexts = 1, \
-       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+       .ppgtt_type = INTEL_PPGTT_FULL, \
+       .ppgtt_size = 48, \
        .has_64bit_reloc = 1, \
        .has_reset_engine = 1
 
@@ -540,7 +544,8 @@ static const struct intel_device_info intel_cherryview_info = {
        .has_rc6 = 1,
        .has_logical_ring_contexts = 1,
        .display.has_gmch = 1,
-       .ppgtt = INTEL_PPGTT_FULL,
+       .ppgtt_type = INTEL_PPGTT_FULL,
+       .ppgtt_size = 32,
        .has_reset_engine = 1,
        .has_snoop = true,
        .has_coherent_ggtt = false,
@@ -616,7 +621,8 @@ static const struct intel_device_info intel_skylake_gt4_info = {
        .has_logical_ring_contexts = 1, \
        .has_logical_ring_preemption = 1, \
        .has_guc = 1, \
-       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+       .ppgtt_type = INTEL_PPGTT_FULL, \
+       .ppgtt_size = 48, \
        .has_reset_engine = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = false, \
@@ -724,6 +730,14 @@ static const struct intel_device_info intel_icelake_11_info = {
                BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 };
 
+static const struct intel_device_info intel_elkhartlake_info = {
+       GEN11_FEATURES,
+       PLATFORM(INTEL_ELKHARTLAKE),
+       .is_alpha_support = 1,
+       .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
+       .ppgtt_size = 36,
+};
+
 #undef GEN
 #undef PLATFORM
 
@@ -789,8 +803,11 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
        INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
        INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
+       INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
+       INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
        INTEL_CNL_IDS(&intel_cannonlake_info),
        INTEL_ICL_11_IDS(&intel_icelake_11_info),
+       INTEL_EHL_IDS(&intel_elkhartlake_info),
        {0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);