Merge tag 'drm-intel-gt-next-2023-05-24' of git://anongit.freedesktop.org/drm/drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_pci.c

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index edcfb5f..75cbccd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -29,6 +29,7 @@
 #include "display/intel_display.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_sa_media.h"
+#include "gem/i915_gem_object_types.h"
 
 #include "i915_driver.h"
 #include "i915_drv.h"
@@ -163,6 +164,38 @@
                .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
        }
 
+#define LEGACY_CACHELEVEL \
+       .cachelevel_to_pat = { \
+               [I915_CACHE_NONE]   = 0, \
+               [I915_CACHE_LLC]    = 1, \
+               [I915_CACHE_L3_LLC] = 2, \
+               [I915_CACHE_WT]     = 3, \
+       }
+
+#define TGL_CACHELEVEL \
+       .cachelevel_to_pat = { \
+               [I915_CACHE_NONE]   = 3, \
+               [I915_CACHE_LLC]    = 0, \
+               [I915_CACHE_L3_LLC] = 0, \
+               [I915_CACHE_WT]     = 2, \
+       }
+
+#define PVC_CACHELEVEL \
+       .cachelevel_to_pat = { \
+               [I915_CACHE_NONE]   = 0, \
+               [I915_CACHE_LLC]    = 3, \
+               [I915_CACHE_L3_LLC] = 3, \
+               [I915_CACHE_WT]     = 2, \
+       }
+
+#define MTL_CACHELEVEL \
+       .cachelevel_to_pat = { \
+               [I915_CACHE_NONE]   = 2, \
+               [I915_CACHE_LLC]    = 3, \
+               [I915_CACHE_L3_LLC] = 3, \
+               [I915_CACHE_WT]     = 1, \
+       }
+
 /* Keep in gen based order, and chronological order within a gen */
 
 #define GEN_DEFAULT_PAGE_SIZES \
@@ -188,11 +221,13 @@
        .has_snoop = true, \
        .has_coherent_ggtt = false, \
        .dma_mask_size = 32, \
+       .max_pat_index = 3, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        I9XX_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 #define I845_FEATURES \
        GEN(2), \
@@ -209,11 +244,13 @@
        .has_snoop = true, \
        .has_coherent_ggtt = false, \
        .dma_mask_size = 32, \
+       .max_pat_index = 3, \
        I845_PIPE_OFFSETS, \
        I845_CURSOR_OFFSETS, \
        I845_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 static const struct intel_device_info i830_info = {
        I830_FEATURES,
@@ -248,11 +285,13 @@ static const struct intel_device_info i865g_info = {
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        .dma_mask_size = 32, \
+       .max_pat_index = 3, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        I9XX_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 static const struct intel_device_info i915g_info = {
        GEN3_FEATURES,
@@ -340,11 +379,13 @@ static const struct intel_device_info pnv_m_info = {
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        .dma_mask_size = 36, \
+       .max_pat_index = 3, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        I9XX_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 static const struct intel_device_info i965g_info = {
        GEN4_FEATURES,
@@ -394,11 +435,13 @@ static const struct intel_device_info gm45_info = {
        /* ilk does support rc6, but we do not implement [power] contexts */ \
        .has_rc6 = 0, \
        .dma_mask_size = 36, \
+       .max_pat_index = 3, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        ILK_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 static const struct intel_device_info ilk_d_info = {
        GEN5_FEATURES,
@@ -428,13 +471,15 @@ static const struct intel_device_info ilk_m_info = {
        .has_rc6p = 0, \
        .has_rps = true, \
        .dma_mask_size = 40, \
+       .max_pat_index = 3, \
        .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
        .__runtime.ppgtt_size = 31, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        ILK_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 #define SNB_D_PLATFORM \
        GEN6_FEATURES, \
@@ -481,13 +526,15 @@ static const struct intel_device_info snb_m_gt2_info = {
        .has_reset_engine = true, \
        .has_rps = true, \
        .dma_mask_size = 40, \
+       .max_pat_index = 3, \
        .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
        .__runtime.ppgtt_size = 31, \
        IVB_PIPE_OFFSETS, \
        IVB_CURSOR_OFFSETS, \
        IVB_COLORS, \
        GEN_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 #define IVB_D_PLATFORM \
        GEN7_FEATURES, \
@@ -541,6 +588,7 @@ static const struct intel_device_info vlv_info = {
        .display.has_gmch = 1,
        .display.has_hotplug = 1,
        .dma_mask_size = 40,
+       .max_pat_index = 3,
        .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
        .__runtime.ppgtt_size = 31,
        .has_snoop = true,
@@ -552,6 +600,7 @@ static const struct intel_device_info vlv_info = {
        I9XX_COLORS,
        GEN_DEFAULT_PAGE_SIZES,
        GEN_DEFAULT_REGIONS,
+       LEGACY_CACHELEVEL,
 };
 
 #define G75_FEATURES  \
@@ -639,6 +688,7 @@ static const struct intel_device_info chv_info = {
        .has_logical_ring_contexts = 1,
        .display.has_gmch = 1,
        .dma_mask_size = 39,
+       .max_pat_index = 3,
        .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
        .__runtime.ppgtt_size = 32,
        .has_reset_engine = 1,
@@ -650,6 +700,7 @@ static const struct intel_device_info chv_info = {
        CHV_COLORS,
        GEN_DEFAULT_PAGE_SIZES,
        GEN_DEFAULT_REGIONS,
+       LEGACY_CACHELEVEL,
 };
 
 #define GEN9_DEFAULT_PAGE_SIZES \
@@ -731,11 +782,13 @@ static const struct intel_device_info skl_gt4_info = {
        .has_snoop = true, \
        .has_coherent_ggtt = false, \
        .display.has_ipc = 1, \
+       .max_pat_index = 3, \
        HSW_PIPE_OFFSETS, \
        IVB_CURSOR_OFFSETS, \
        IVB_COLORS, \
        GEN9_DEFAULT_PAGE_SIZES, \
-       GEN_DEFAULT_REGIONS
+       GEN_DEFAULT_REGIONS, \
+       LEGACY_CACHELEVEL
 
 static const struct intel_device_info bxt_info = {
        GEN9_LP_FEATURES,
@@ -889,9 +942,11 @@ static const struct intel_device_info jsl_info = {
                [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
        }, \
        TGL_CURSOR_OFFSETS, \
+       TGL_CACHELEVEL, \
        .has_global_mocs = 1, \
        .has_pxp = 1, \
-       .display.has_dsb = 1
+       .display.has_dsb = 1, \
+       .max_pat_index = 3
 
 static const struct intel_device_info tgl_info = {
        GEN12_FEATURES,
@@ -1013,6 +1068,7 @@ static const struct intel_device_info adl_p_info = {
        .__runtime.graphics.ip.ver = 12, \
        .__runtime.graphics.ip.rel = 50, \
        XE_HP_PAGE_SIZES, \
+       TGL_CACHELEVEL, \
        .dma_mask_size = 46, \
        .has_3d_pipeline = 1, \
        .has_64bit_reloc = 1, \
@@ -1031,6 +1087,7 @@ static const struct intel_device_info adl_p_info = {
        .has_reset_engine = 1, \
        .has_rps = 1, \
        .has_runtime_pm = 1, \
+       .max_pat_index = 3, \
        .__runtime.ppgtt_size = 48, \
        .__runtime.ppgtt_type = INTEL_PPGTT_FULL
 
@@ -1107,11 +1164,13 @@ static const struct intel_device_info pvc_info = {
        PLATFORM(INTEL_PONTEVECCHIO),
        NO_DISPLAY,
        .has_flat_ccs = 0,
+       .max_pat_index = 7,
        .__runtime.platform_engine_mask =
                BIT(BCS0) |
                BIT(VCS0) |
                BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
        .require_force_probe = 1,
+       PVC_CACHELEVEL,
 };
 
 #define XE_LPDP_FEATURES       \
@@ -1148,11 +1207,15 @@ static const struct intel_device_info mtl_info = {
        .has_flat_ccs = 0,
        .has_gmd_id = 1,
        .has_guc_deprivilege = 1,
+       .has_llc = 0,
        .has_mslice_steering = 0,
        .has_snoop = 1,
+       .max_pat_index = 4,
+       .has_pxp = 1,
        .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
        .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
        .require_force_probe = 1,
+       MTL_CACHELEVEL,
 };
 
 #undef PLATFORM