drm/i915: Handle cdclk crawling flag in standard manner

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_pci.c

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4805537..0c11c0e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -36,7 +36,10 @@
 #include "i915_selftest.h"
 
 #define PLATFORM(x) .platform = (x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.version = (x)
+#define GEN(x) \
+       .graphics_ver = (x), \
+       .media_ver = (x), \
+       .display.ver = (x)
 
 #define I845_PIPE_OFFSETS \
        .pipe_offsets = { \
@@ -640,12 +643,12 @@ static const struct intel_device_info chv_info = {
        GEN8_FEATURES, \
        GEN(9), \
        GEN9_DEFAULT_PAGE_SIZES, \
-       .display.has_csr = 1, \
+       .display.has_dmc = 1, \
        .has_gt_uc = 1, \
        .display.has_hdcp = 1, \
        .display.has_ipc = 1, \
-       .ddb_size = 896, \
-       .num_supported_dbuf_slices = 1
+       .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+       .dbuf.slice_mask = BIT(DBUF_S1)
 
 #define SKL_PLATFORM \
        GEN9_FEATURES, \
@@ -680,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
 #define GEN9_LP_FEATURES \
        GEN(9), \
        .is_lp = 1, \
-       .num_supported_dbuf_slices = 1, \
+       .dbuf.slice_mask = BIT(DBUF_S1), \
        .display.has_hotplug = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
        .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -695,7 +698,7 @@ static const struct intel_device_info skl_gt4_info = {
        .display.has_psr = 1, \
        .display.has_psr_hw_tracking = 1, \
        .has_runtime_pm = 1, \
-       .display.has_csr = 1, \
+       .display.has_dmc = 1, \
        .has_rc6 = 1, \
        .has_rps = true, \
        .display.has_dp_mst = 1, \
@@ -717,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
 static const struct intel_device_info bxt_info = {
        GEN9_LP_FEATURES,
        PLATFORM(INTEL_BROXTON),
-       .ddb_size = 512,
+       .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 };
 
 static const struct intel_device_info glk_info = {
        GEN9_LP_FEATURES,
        PLATFORM(INTEL_GEMINILAKE),
-       .display.version = 10,
-       .ddb_size = 1024,
+       .display.ver = 10,
+       .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
        GLK_COLORS,
 };
 
@@ -787,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN10_FEATURES \
        GEN9_FEATURES, \
        GEN(10), \
-       .ddb_size = 1024, \
+       .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
        .display.has_dsc = 1, \
        .has_coherent_ggtt = false, \
        GLK_COLORS
@@ -827,8 +830,8 @@ static const struct intel_device_info cnl_info = {
                [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
        }, \
        GEN(11), \
-       .ddb_size = 2048, \
-       .num_supported_dbuf_slices = 2, \
+       .dbuf.size = 2048, \
+       .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
        .has_logical_ring_elsq = 1, \
        .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
 
@@ -842,7 +845,6 @@ static const struct intel_device_info icl_info = {
 static const struct intel_device_info ehl_info = {
        GEN11_FEATURES,
        PLATFORM(INTEL_ELKHARTLAKE),
-       .require_force_probe = 1,
        .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
        .ppgtt_size = 36,
 };
@@ -850,7 +852,6 @@ static const struct intel_device_info ehl_info = {
 static const struct intel_device_info jsl_info = {
        GEN11_FEATURES,
        PLATFORM(INTEL_JASPERLAKE),
-       .require_force_probe = 1,
        .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
        .ppgtt_size = 36,
 };
@@ -904,16 +905,16 @@ static const struct intel_device_info rkl_info = {
                BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
 
-#define GEN12_DGFX_FEATURES \
-       GEN12_FEATURES, \
-       .memory_regions = REGION_SMEM | REGION_LMEM, \
+#define DGFX_FEATURES \
+       .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
        .has_master_unit_irq = 1, \
        .has_llc = 0, \
        .has_snoop = 1, \
        .is_dgfx = 1
 
 static const struct intel_device_info dg1_info __maybe_unused = {
-       GEN12_DGFX_FEATURES,
+       GEN12_FEATURES,
+       DGFX_FEATURES,
        PLATFORM(INTEL_DG1),
        .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
        .require_force_probe = 1,
@@ -936,6 +937,63 @@ static const struct intel_device_info adl_s_info = {
        .dma_mask_size = 46,
 };
 
+#define XE_LPD_CURSOR_OFFSETS \
+       .cursor_offsets = { \
+               [PIPE_A] = CURSOR_A_OFFSET, \
+               [PIPE_B] = IVB_CURSOR_B_OFFSET, \
+               [PIPE_C] = IVB_CURSOR_C_OFFSET, \
+               [PIPE_D] = TGL_CURSOR_D_OFFSET, \
+       }
+
+#define XE_LPD_FEATURES \
+       .abox_mask = GENMASK(1, 0),                                             \
+       .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 },          \
+       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |          \
+               BIT(TRANSCODER_C) | BIT(TRANSCODER_D),                          \
+       .dbuf.size = 4096,                                                      \
+       .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
+               BIT(DBUF_S4),                                                   \
+       .display.has_ddi = 1,                                                   \
+       .display.has_dmc = 1,                                                   \
+       .display.has_dp_mst = 1,                                                \
+       .display.has_dsb = 1,                                                   \
+       .display.has_dsc = 1,                                                   \
+       .display.has_fbc = 1,                                                   \
+       .display.has_fpga_dbg = 1,                                              \
+       .display.has_hdcp = 1,                                                  \
+       .display.has_hotplug = 1,                                               \
+       .display.has_ipc = 1,                                                   \
+       .display.has_psr = 1,                                                   \
+       .display.ver = 13,                                                      \
+       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
+       .pipe_offsets = {                                                       \
+               [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
+               [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
+               [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
+               [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
+       },                                                                      \
+       .trans_offsets = {                                                      \
+               [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
+               [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
+               [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
+               [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
+       },                                                                      \
+       XE_LPD_CURSOR_OFFSETS
+
+static const struct intel_device_info adl_p_info = {
+       GEN12_FEATURES,
+       XE_LPD_FEATURES,
+       PLATFORM(INTEL_ALDERLAKE_P),
+       .require_force_probe = 1,
+       .display.has_cdclk_crawl = 1,
+       .display.has_modular_fia = 1,
+       .display.has_psr_hw_tracking = 0,
+       .platform_engine_mask =
+               BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+       .ppgtt_size = 48,
+       .dma_mask_size = 39,
+};
+
 #undef GEN
 #undef PLATFORM
 
@@ -1013,6 +1071,7 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_TGL_12_IDS(&tgl_info),
        INTEL_RKL_IDS(&rkl_info),
        INTEL_ADLS_IDS(&adl_s_info),
+       INTEL_ADLP_IDS(&adl_p_info),
        {0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);