Merge tag 'powerpc-5.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gvt / vgpu.c

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 7d36162..8fa9b31 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -257,6 +257,7 @@ void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
        intel_gvt_deactivate_vgpu(vgpu);
 
        mutex_lock(&vgpu->vgpu_lock);
+       vgpu->d3_entered = false;
        intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
        intel_vgpu_dmabuf_cleanup(vgpu);
        mutex_unlock(&vgpu->vgpu_lock);
@@ -393,6 +394,7 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
        INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
        idr_init(&vgpu->object_idr);
        intel_vgpu_init_cfg_space(vgpu, param->primary);
+       vgpu->d3_entered = false;
 
        ret = intel_vgpu_init_mmio(vgpu);
        if (ret)
@@ -557,10 +559,15 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
        /* full GPU reset or device model level reset */
        if (engine_mask == ALL_ENGINES || dmlr) {
                intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
-               intel_vgpu_invalidate_ppgtt(vgpu);
+               if (engine_mask == ALL_ENGINES)
+                       intel_vgpu_invalidate_ppgtt(vgpu);
                /*fence will not be reset during virtual reset */
                if (dmlr) {
-                       intel_vgpu_reset_gtt(vgpu);
+                       if(!vgpu->d3_entered) {
+                               intel_vgpu_invalidate_ppgtt(vgpu);
+                               intel_vgpu_destroy_all_ppgtt_mm(vgpu);
+                       }
+                       intel_vgpu_reset_ggtt(vgpu, true);
                        intel_vgpu_reset_resource(vgpu);
                }
 
@@ -572,7 +579,14 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
                        intel_vgpu_reset_cfg_space(vgpu);
                        /* only reset the failsafe mode when dmlr reset */
                        vgpu->failsafe = false;
-                       vgpu->pv_notified = false;
+                       /*
+                        * PCI_D0 is set before dmlr, so reset d3_entered here
+                        * after done using.
+                        */
+                       if(vgpu->d3_entered)
+                               vgpu->d3_entered = false;
+                       else
+                               vgpu->pv_notified = false;
                }
        }