Merge tag 'gvt-next-2020-03-10' of https://github.com/intel/gvt-linux into drm-intel...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gvt / interrupt.c

diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 11accd3..540017f 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -245,6 +245,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
        unsigned int reg, void *p_data, unsigned int bytes)
 {
        struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *i915 = gvt->gt->i915;
        struct intel_gvt_irq_ops *ops = gvt->irq.ops;
        struct intel_gvt_irq_info *info;
        u32 ier = *(u32 *)p_data;
@@ -255,7 +256,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
        vgpu_vreg(vgpu, reg) = ier;
 
        info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
-       if (WARN_ON(!info))
+       if (drm_WARN_ON(&i915->drm, !info))
                return -EINVAL;
 
        if (info->has_upstream_irq)
@@ -282,6 +283,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
        void *p_data, unsigned int bytes)
 {
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
        struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
                iir_to_regbase(reg));
        u32 iir = *(u32 *)p_data;
@@ -289,7 +291,7 @@ int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
        trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
                       (vgpu_vreg(vgpu, reg) ^ iir));
 
-       if (WARN_ON(!info))
+       if (drm_WARN_ON(&i915->drm, !info))
                return -EINVAL;
 
        vgpu_vreg(vgpu, reg) &= ~iir;
@@ -319,6 +321,7 @@ static struct intel_gvt_irq_map gen8_irq_map[] = {
 static void update_upstream_irq(struct intel_vgpu *vgpu,
                struct intel_gvt_irq_info *info)
 {
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
        struct intel_gvt_irq *irq = &vgpu->gvt->irq;
        struct intel_gvt_irq_map *map = irq->irq_map;
        struct intel_gvt_irq_info *up_irq_info = NULL;
@@ -340,7 +343,8 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
                if (!up_irq_info)
                        up_irq_info = irq->info[map->up_irq_group];
                else
-                       WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
+                       drm_WARN_ON(&i915->drm, up_irq_info !=
+                                   irq->info[map->up_irq_group]);
 
                bit = map->up_irq_bit;
 
@@ -350,7 +354,7 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
                        clear_bits |= (1 << bit);
        }
 
-       if (WARN_ON(!up_irq_info))
+       if (drm_WARN_ON(&i915->drm, !up_irq_info))
                return;
 
        if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
@@ -536,7 +540,7 @@ static void gen8_init_irq(
        SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
        SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
 
-       if (HAS_ENGINE(gvt->dev_priv, VCS1)) {
+       if (HAS_ENGINE(gvt->gt->i915, VCS1)) {
                SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
                        INTEL_GVT_IRQ_INFO_GT1);
                SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
@@ -568,7 +572,7 @@ static void gen8_init_irq(
        SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
        SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
 
-       if (IS_BROADWELL(gvt->dev_priv)) {
+       if (IS_BROADWELL(gvt->gt->i915)) {
                SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
                SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
                SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
@@ -581,7 +585,7 @@ static void gen8_init_irq(
 
                SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
                SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
-       } else if (INTEL_GEN(gvt->dev_priv) >= 9) {
+       } else if (INTEL_GEN(gvt->gt->i915) >= 9) {
                SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
                SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
                SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
@@ -618,13 +622,14 @@ static struct intel_gvt_irq_ops gen8_irq_ops = {
 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
        enum intel_gvt_event_type event)
 {
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
        struct intel_gvt *gvt = vgpu->gvt;
        struct intel_gvt_irq *irq = &gvt->irq;
        gvt_event_virt_handler_t handler;
        struct intel_gvt_irq_ops *ops = gvt->irq.ops;
 
        handler = get_event_virt_handler(irq, event);
-       WARN_ON(!handler);
+       drm_WARN_ON(&i915->drm, !handler);
 
        handler(irq, event, vgpu);