Merge tag 'drm-intel-gt-next-2021-04-06' of git://anongit.freedesktop.org/drm/drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gt / selftest_mocs.c

diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index f00b914..e55a887 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -1,6 +1,5 @@
+// SPDX-License-Identifier: MIT
 /*
- * SPDX-License-Identifier: MIT
- *
  * Copyright © 2019 Intel Corporation
  */
 
@@ -13,8 +12,9 @@
 #include "selftests/igt_spinner.h"
 
 struct live_mocs {
-       struct drm_i915_mocs_table mocs;
-       struct drm_i915_mocs_table l3cc;
+       struct drm_i915_mocs_table table;
+       struct drm_i915_mocs_table *mocs;
+       struct drm_i915_mocs_table *l3cc;
        struct i915_vma *scratch;
        void *vaddr;
 };
@@ -59,21 +59,20 @@ static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
 
 static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
 {
-       struct drm_i915_mocs_table table;
        unsigned int flags;
        int err;
 
        memset(arg, 0, sizeof(*arg));
 
-       flags = get_mocs_settings(gt->i915, &table);
+       flags = get_mocs_settings(gt->i915, &arg->table);
        if (!flags)
                return -EINVAL;
 
        if (flags & HAS_RENDER_L3CC)
-               arg->l3cc = table;
+               arg->l3cc = &arg->table;
 
        if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
-               arg->mocs = table;
+               arg->mocs = &arg->table;
 
        arg->scratch =
                __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE);
@@ -132,6 +131,9 @@ static int read_mocs_table(struct i915_request *rq,
 {
        u32 addr;
 
+       if (!table)
+               return 0;
+
        if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
                addr = global_mocs_offset();
        else
@@ -146,6 +148,9 @@ static int read_l3cc_table(struct i915_request *rq,
 {
        u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
 
+       if (!table)
+               return 0;
+
        return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
 }
 
@@ -156,6 +161,9 @@ static int check_mocs_table(struct intel_engine_cs *engine,
        unsigned int i;
        u32 expect;
 
+       if (!table)
+               return 0;
+
        for_each_mocs(expect, table, i) {
                if (**vaddr != expect) {
                        pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
@@ -187,6 +195,9 @@ static int check_l3cc_table(struct intel_engine_cs *engine,
        unsigned int i;
        u32 expect;
 
+       if (!table)
+               return 0;
+
        for_each_l3cc(expect, table, i) {
                if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
                        pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
@@ -224,9 +235,9 @@ static int check_mocs_engine(struct live_mocs *arg,
        /* Read the mocs tables back using SRM */
        offset = i915_ggtt_offset(vma);
        if (!err)
-               err = read_mocs_table(rq, &arg->mocs, &offset);
+               err = read_mocs_table(rq, arg->mocs, &offset);
        if (!err && ce->engine->class == RENDER_CLASS)
-               err = read_l3cc_table(rq, &arg->l3cc, &offset);
+               err = read_l3cc_table(rq, arg->l3cc, &offset);
        offset -= i915_ggtt_offset(vma);
        GEM_BUG_ON(offset > PAGE_SIZE);
 
@@ -237,9 +248,9 @@ static int check_mocs_engine(struct live_mocs *arg,
        /* Compare the results against the expected tables */
        vaddr = arg->vaddr;
        if (!err)
-               err = check_mocs_table(ce->engine, &arg->mocs, &vaddr);
+               err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
        if (!err && ce->engine->class == RENDER_CLASS)
-               err = check_l3cc_table(ce->engine, &arg->l3cc, &vaddr);
+               err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
        if (err)
                return err;