Merge tag 'drm-next-2020-12-11' of git://anongit.freedesktop.org/drm/drm

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gt / intel_mocs.c

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 4f74706..ab68702 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -59,8 +59,7 @@ struct drm_i915_mocs_table {
 #define _L3_CACHEABILITY(value)        ((value) << 4)
 
 /* Helper defines */
-#define GEN9_NUM_MOCS_ENTRIES  62  /* 62 out of 64 - 63 & 64 are reserved. */
-#define GEN11_NUM_MOCS_ENTRIES 64  /* 63-64 are reserved, but configured. */
+#define GEN9_NUM_MOCS_ENTRIES  64  /* 63-64 are reserved, but configured. */
 
 /* (e)LLC caching options */
 /*
@@ -109,7 +108,7 @@ struct drm_i915_mocs_table {
  * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
  * PTE and will be initialized to an invalid value.
  *
- * The last two entries are reserved by the hardware. For ICL+ they
+ * The last few entries are reserved by the hardware. For ICL+ they
  * should be initialized according to bspec and never used, for older
  * platforms they should never be written to.
  *
@@ -124,7 +123,7 @@ struct drm_i915_mocs_table {
                   LE_1_UC | LE_TC_2_LLC_ELLC, \
                   L3_1_UC), \
        MOCS_ENTRY(I915_MOCS_PTE, \
-                  LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
+                  LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
                   L3_3_WB)
 
 static const struct drm_i915_mocs_entry skl_mocs_table[] = {
@@ -293,12 +292,45 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
                   L3_1_UC),
        /* Base - L3 + LeCC:PAT (Deprecated) */
        MOCS_ENTRY(I915_MOCS_PTE,
-                  LE_0_PAGETABLE | LE_TC_1_LLC,
+                  LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
                   L3_3_WB),
 
        GEN11_MOCS_ENTRIES
 };
 
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+       /* Error */
+       MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+       /* UC */
+       MOCS_ENTRY(1, 0, L3_1_UC),
+
+       /* Reserved */
+       MOCS_ENTRY(2, 0, L3_0_DIRECT),
+       MOCS_ENTRY(3, 0, L3_0_DIRECT),
+       MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+       /* WB - L3 */
+       MOCS_ENTRY(5, 0, L3_3_WB),
+       /* WB - L3 50% */
+       MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+       /* WB - L3 25% */
+       MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+       /* WB - L3 12.5% */
+       MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+       /* HDC:L1 + L3 */
+       MOCS_ENTRY(48, 0, L3_3_WB),
+       /* HDC:L1 */
+       MOCS_ENTRY(49, 0, L3_1_UC),
+
+       /* HW Reserved */
+       MOCS_ENTRY(60, 0, L3_1_UC),
+       MOCS_ENTRY(61, 0, L3_1_UC),
+       MOCS_ENTRY(62, 0, L3_1_UC),
+       MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
 enum {
        HAS_GLOBAL_MOCS = BIT(0),
        HAS_ENGINE_MOCS = BIT(1),
@@ -325,14 +357,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
        unsigned int flags;
 
-       if (INTEL_GEN(i915) >= 12) {
+       if (IS_DG1(i915)) {
+               table->size = ARRAY_SIZE(dg1_mocs_table);
+               table->table = dg1_mocs_table;
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+       } else if (INTEL_GEN(i915) >= 12) {
                table->size  = ARRAY_SIZE(tgl_mocs_table);
                table->table = tgl_mocs_table;
-               table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
        } else if (IS_GEN(i915, 11)) {
                table->size  = ARRAY_SIZE(icl_mocs_table);
                table->table = icl_mocs_table;
-               table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
        } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
                table->size  = ARRAY_SIZE(skl_mocs_table);
                table->n_entries = GEN9_NUM_MOCS_ENTRIES;