Merge tag 'drm-intel-gt-next-2021-04-06' of git://anongit.freedesktop.org/drm/drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gt / intel_gtt.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 8f7c49e..e67e34e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -85,6 +85,10 @@ typedef u64 gen8_pte_t;
 #define BYT_PTE_SNOOPED_BY_CPU_CACHES  REG_BIT(2)
 #define BYT_PTE_WRITEABLE              REG_BIT(1)
 
+#define GEN12_PPGTT_PTE_LM     BIT_ULL(11)
+
+#define GEN12_GGTT_PTE_LM      BIT_ULL(1)
+
 /*
  * Cacheability Control is a 4-bit value. The low three bits are stored in bits
  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
@@ -265,6 +269,7 @@ struct i915_address_space {
                          enum i915_cache_level level,
                          u32 flags); /* Create a valid PTE */
 #define PTE_READ_ONLY  BIT(0)
+#define PTE_LM         BIT(1)
 
        void (*allocate_va_range)(struct i915_address_space *vm,
                                  struct i915_vm_pt_stash *stash,