Merge tag 'drm-intel-next-2023-03-07' of git://anongit.freedesktop.org/drm/drm-intel...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gt / intel_gt_regs.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 49a614b..df07e1e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -405,6 +405,8 @@
 #define GEN9_WM_CHICKEN3                       _MMIO(0x5588)
 #define   GEN9_FACTOR_IN_CLR_VAL_HIZ           (1 << 9)
 
+#define XEHP_CULLBIT1                          MCR_REG(0x6100)
+
 #define CHICKEN_RASTER_1                       MCR_REG(0x6204)
 #define   DIS_SF_ROUND_NEAREST_EVEN            REG_BIT(8)
 
@@ -455,10 +457,12 @@
 #define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE      REG_BIT(13)
 #define   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE  REG_BIT(3)
 
+#define XEHP_CULLBIT2                          MCR_REG(0x7030)
+
 #define GEN8_L3CNTLREG                         _MMIO(0x7034)
 #define   GEN8_ERRDETBCTRL                     (1 << 9)
 
-#define PSS_MODE2                              _MMIO(0x703c)
+#define XEHP_PSS_MODE2                         MCR_REG(0x703c)
 #define   SCOREBOARD_STALL_FLUSH_CONTROL       REG_BIT(5)
 
 #define GEN7_SC_INSTDONE                       _MMIO(0x7100)
@@ -680,10 +684,7 @@
 #define GEN6_RSTCTL                            _MMIO(0x9420)
 
 #define GEN7_MISCCPCTL                         _MMIO(0x9424)
-#define   GEN7_DOP_CLOCK_GATE_ENABLE           (1 << 0)
-
-#define GEN8_MISCCPCTL                         MCR_REG(0x9424)
-#define   GEN8_DOP_CLOCK_GATE_ENABLE           REG_BIT(0)
+#define   GEN7_DOP_CLOCK_GATE_ENABLE           REG_BIT(0)
 #define   GEN12_DOP_CLOCK_GATE_RENDER_ENABLE   REG_BIT(1)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE     (1 << 2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE       (1 << 4)
@@ -973,7 +974,7 @@
 #define   GEN7_WA_FOR_GEN7_L3_CONTROL          0x3C47FF8C
 #define   GEN7_L3AGDIS                         (1 << 19)
 
-#define XEHPC_LNCFMISCCFGREG0                  _MMIO(0xb01c)
+#define XEHPC_LNCFMISCCFGREG0                  MCR_REG(0xb01c)
 #define   XEHPC_HOSTCACHEEN                    REG_BIT(1)
 #define   XEHPC_OVRLSCCC                       REG_BIT(0)
 
@@ -1036,7 +1037,7 @@
 #define XEHP_L3SCQREG7                         MCR_REG(0xb188)
 #define   BLEND_FILL_CACHING_OPT_DIS           REG_BIT(3)
 
-#define XEHPC_L3SCRUB                          _MMIO(0xb18c)
+#define XEHPC_L3SCRUB                          MCR_REG(0xb18c)
 #define   SCRUB_CL_DWNGRADE_SHARED             REG_BIT(12)
 #define   SCRUB_RATE_PER_BANK_MASK             REG_GENMASK(2, 0)
 #define   SCRUB_RATE_4B_PER_CLK                        REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
@@ -1094,16 +1095,19 @@
 #define XEHP_MERT_MOD_CTRL                     MCR_REG(0xcf28)
 #define RENDER_MOD_CTRL                                MCR_REG(0xcf2c)
 #define COMP_MOD_CTRL                          MCR_REG(0xcf30)
-#define VDBX_MOD_CTRL                          MCR_REG(0xcf34)
-#define VEBX_MOD_CTRL                          MCR_REG(0xcf38)
+#define XELPMP_GSC_MOD_CTRL                    _MMIO(0xcf30)   /* media GT only */
+#define XEHP_VDBX_MOD_CTRL                     MCR_REG(0xcf34)
+#define XELPMP_VDBX_MOD_CTRL                   _MMIO(0xcf34)
+#define XEHP_VEBX_MOD_CTRL                     MCR_REG(0xcf38)
+#define XELPMP_VEBX_MOD_CTRL                   _MMIO(0xcf38)
 #define   FORCE_MISS_FTLB                      REG_BIT(3)
 
-#define GEN12_GAMSTLB_CTRL                     _MMIO(0xcf4c)
+#define XEHP_GAMSTLB_CTRL                      MCR_REG(0xcf4c)
 #define   CONTROL_BLOCK_CLKGATE_DIS            REG_BIT(12)
 #define   EGRESS_BLOCK_CLKGATE_DIS             REG_BIT(11)
 #define   TAG_BLOCK_CLKGATE_DIS                        REG_BIT(7)
 
-#define GEN12_GAMCNTRL_CTRL                    _MMIO(0xcf54)
+#define XEHP_GAMCNTRL_CTRL                     MCR_REG(0xcf54)
 #define   INVALIDATION_BROADCAST_MODE_DIS      REG_BIT(12)
 #define   GLOBAL_INVALIDATION_MODE             REG_BIT(2)