drm/i915/gt: Pipelined page migration

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gt / intel_engine.h

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 760fefd..62f7440 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -13,13 +13,15 @@
 #include "i915_reg.h"
 #include "i915_request.h"
 #include "i915_selftest.h"
-#include "gt/intel_timeline.h"
 #include "intel_engine_types.h"
-#include "intel_gpu_commands.h"
+#include "intel_gt_types.h"
+#include "intel_timeline.h"
 #include "intel_workarounds.h"
 
 struct drm_printer;
+struct intel_context;
 struct intel_gt;
+struct lock_class_key;
 
 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -186,6 +188,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 #define I915_GEM_HWS_PREEMPT_ADDR      (I915_GEM_HWS_PREEMPT * sizeof(u32))
 #define I915_GEM_HWS_SEQNO             0x40
 #define I915_GEM_HWS_SEQNO_ADDR                (I915_GEM_HWS_SEQNO * sizeof(u32))
+#define I915_GEM_HWS_MIGRATE           (0x42 * sizeof(u32))
 #define I915_GEM_HWS_SCRATCH           0x80
 
 #define I915_HWS_CSB_BUF0_INDEX                0x10
@@ -223,91 +226,6 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
 
 void intel_engine_init_execlists(struct intel_engine_cs *engine);
 
-static inline u32 *__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
-{
-       memset(batch, 0, 6 * sizeof(u32));
-
-       batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
-       batch[1] = flags1;
-       batch[2] = offset;
-
-       return batch + 6;
-}
-
-static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
-{
-       return __gen8_emit_pipe_control(batch, 0, flags, offset);
-}
-
-static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
-{
-       return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
-}
-
-static inline u32 *
-__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
-{
-       *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
-       *cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
-       *cs++ = offset;
-       *cs++ = 0;
-       *cs++ = value;
-       *cs++ = 0; /* We're thrashing one extra dword. */
-
-       return cs;
-}
-
-static inline u32*
-gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
-{
-       /* We're using qword write, offset should be aligned to 8 bytes. */
-       GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
-
-       return __gen8_emit_write_rcs(cs,
-                                    value,
-                                    gtt_offset,
-                                    0,
-                                    flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
-}
-
-static inline u32*
-gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
-{
-       /* We're using qword write, offset should be aligned to 8 bytes. */
-       GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
-
-       return __gen8_emit_write_rcs(cs,
-                                    value,
-                                    gtt_offset,
-                                    flags0,
-                                    flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
-}
-
-static inline u32 *
-__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
-{
-       *cs++ = (MI_FLUSH_DW + 1) | flags;
-       *cs++ = gtt_offset;
-       *cs++ = 0;
-       *cs++ = value;
-
-       return cs;
-}
-
-static inline u32 *
-gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
-{
-       /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
-       GEM_BUG_ON(gtt_offset & (1 << 5));
-       /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
-       GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
-
-       return __gen8_emit_flush_dw(cs,
-                                   value,
-                                   gtt_offset | MI_FLUSH_DW_USE_GTT,
-                                   flags | MI_FLUSH_DW_OP_STOREDW);
-}
-
 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
                                        bool stalled)
 {
@@ -318,7 +236,12 @@ static inline void __intel_engine_reset(struct intel_engine_cs *engine,
 
 bool intel_engines_are_idle(struct intel_gt *gt);
 bool intel_engine_is_idle(struct intel_engine_cs *engine);
-void intel_engine_flush_submission(struct intel_engine_cs *engine);
+
+void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);
+static inline void intel_engine_flush_submission(struct intel_engine_cs *engine)
+{
+       __intel_engine_flush_submission(engine, true);
+}
 
 void intel_engines_reset_default_submission(struct intel_gt *gt);
 
@@ -336,6 +259,15 @@ struct i915_request *
 intel_engine_find_active_request(struct intel_engine_cs *engine);
 
 u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+                                  struct i915_address_space *vm,
+                                  unsigned int ring_size,
+                                  unsigned int hwsp,
+                                  struct lock_class_key *key,
+                                  const char *name);
+
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
 
 void intel_engine_init_active(struct intel_engine_cs *engine,
                              unsigned int subclass);
@@ -343,6 +275,11 @@ void intel_engine_init_active(struct intel_engine_cs *engine,
 #define ENGINE_MOCK    1
 #define ENGINE_VIRTUAL 2
 
+static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
+{
+       return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
+}
+
 static inline bool
 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
 {