drm/i915: Have pfit calculations return an error code
[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / display / intel_dp.c
index e169463..5c7009b 100644 (file)
@@ -48,7 +48,6 @@
 #include "intel_audio.h"
 #include "intel_connector.h"
 #include "intel_ddi.h"
-#include "intel_display_debugfs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
@@ -1391,7 +1390,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
         * lowest possible wakeup latency and so prevent the cpu from going into
         * deep sleep states.
         */
-       pm_qos_update_request(&i915->pm_qos, 0);
+       cpu_latency_qos_update_request(&i915->pm_qos, 0);
 
        intel_dp_check_edp(intel_dp);
 
@@ -1524,7 +1523,7 @@ done:
 
        ret = recv_bytes;
 out:
-       pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+       cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
 
        if (vdd)
                edp_panel_vdd_off(intel_dp, false);
@@ -2340,15 +2339,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 
 static int
 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
-                        struct drm_connector *connector,
-                        struct intel_crtc_state *crtc_state)
+                        struct intel_crtc_state *crtc_state,
+                        const struct drm_connector_state *conn_state)
 {
-       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+       struct drm_connector *connector = conn_state->connector;
        const struct drm_display_info *info = &connector->display_info;
        const struct drm_display_mode *adjusted_mode =
                &crtc_state->hw.adjusted_mode;
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-       int ret;
 
        if (!drm_mode_is_420_only(info, adjusted_mode) ||
            !intel_dp_get_colorimetry_status(intel_dp) ||
@@ -2357,17 +2354,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
 
        crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
 
-       /* YCBCR 420 output conversion needs a scaler */
-       ret = skl_update_scaler_crtc(crtc_state);
-       if (ret) {
-               drm_dbg_kms(&i915->drm,
-                           "Scaler allocation for output failed\n");
-               return ret;
-       }
-
-       intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
-
-       return 0;
+       return intel_pch_panel_fitting(crtc_state, conn_state);
 }
 
 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
@@ -2546,7 +2533,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
        enum port port = encoder->port;
-       struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct intel_digital_connector_state *intel_conn_state =
                to_intel_digital_connector_state(conn_state);
@@ -2562,9 +2548,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
        if (lspcon->active)
                lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
        else
-               ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
-                                              pipe_config);
-
+               ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
+                                              conn_state);
        if (ret)
                return ret;
 
@@ -2580,18 +2565,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
                intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
                                       adjusted_mode);
 
-               if (INTEL_GEN(dev_priv) >= 9) {
-                       ret = skl_update_scaler_crtc(pipe_config);
-                       if (ret)
-                               return ret;
-               }
-
                if (HAS_GMCH(dev_priv))
-                       intel_gmch_panel_fitting(intel_crtc, pipe_config,
-                                                conn_state->scaling_mode);
+                       ret = intel_gmch_panel_fitting(pipe_config, conn_state);
                else
-                       intel_pch_panel_fitting(intel_crtc, pipe_config,
-                                               conn_state->scaling_mode);
+                       ret = intel_pch_panel_fitting(pipe_config, conn_state);
+               if (ret)
+                       return ret;
        }
 
        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -2671,9 +2650,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
                                 intel_crtc_has_type(pipe_config,
                                                     INTEL_OUTPUT_DP_MST));
 
-       intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
-       intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
-
        /*
         * There are four kinds of DP registers:
         *
@@ -5401,9 +5377,180 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
        return test_result;
 }
 
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+       struct drm_dp_phy_test_params *data =
+               &intel_dp->compliance.test_data.phytest;
+
+       if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+               DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+               return DP_TEST_NAK;
+       }
+
+       /*
+        * link_mst is set to false to avoid executing mst related code
+        * during compliance testing.
+        */
+       intel_dp->link_mst = false;
+
+       return DP_TEST_ACK;
+}
+
+static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+       struct drm_i915_private *dev_priv =
+                       to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       struct drm_dp_phy_test_params *data =
+                       &intel_dp->compliance.test_data.phytest;
+       struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+       enum pipe pipe = crtc->pipe;
+       u32 pattern_val;
+
+       switch (data->phy_pattern) {
+       case DP_PHY_TEST_PATTERN_NONE:
+               DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+               break;
+       case DP_PHY_TEST_PATTERN_D10_2:
+               DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+                              DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+               break;
+       case DP_PHY_TEST_PATTERN_ERROR_COUNT:
+               DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+                              DDI_DP_COMP_CTL_ENABLE |
+                              DDI_DP_COMP_CTL_SCRAMBLED_0);
+               break;
+       case DP_PHY_TEST_PATTERN_PRBS7:
+               DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+                              DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+               break;
+       case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+               /*
+                * FIXME: Ideally pattern should come from DPCD 0x250. As
+                * current firmware of DPR-100 could not set it, so hardcoding
+                * now for complaince test.
+                */
+               DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
+               pattern_val = 0x3e0f83e0;
+               intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+               pattern_val = 0x0f83e0f8;
+               intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+               pattern_val = 0x0000f83e;
+               intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+                              DDI_DP_COMP_CTL_ENABLE |
+                              DDI_DP_COMP_CTL_CUSTOM80);
+               break;
+       case DP_PHY_TEST_PATTERN_CP2520:
+               /*
+                * FIXME: Ideally pattern should come from DPCD 0x24A. As
+                * current firmware of DPR-100 could not set it, so hardcoding
+                * now for complaince test.
+                */
+               DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+               pattern_val = 0xFB;
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+                              DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+                              pattern_val);
+               break;
+       default:
+               WARN(1, "Invalid Phy Test Pattern\n");
+       }
+}
+
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       struct drm_device *dev = intel_dig_port->base.base.dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+       enum pipe pipe = crtc->pipe;
+       u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+
+       trans_ddi_func_ctl_value = intel_de_read(dev_priv,
+                                                TRANS_DDI_FUNC_CTL(pipe));
+       trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
+       dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
+
+       trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+                                     TGL_TRANS_DDI_PORT_MASK);
+       trans_conf_value &= ~PIPECONF_ENABLE;
+       dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
+
+       intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
+       intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
+                      trans_ddi_func_ctl_value);
+       intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       struct drm_device *dev = intel_dig_port->base.base.dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
+       enum port port = intel_dig_port->base.port;
+       struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+       enum pipe pipe = crtc->pipe;
+       u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+
+       trans_ddi_func_ctl_value = intel_de_read(dev_priv,
+                                                TRANS_DDI_FUNC_CTL(pipe));
+       trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
+       dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
+
+       trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+                                   TGL_TRANS_DDI_SELECT_PORT(port);
+       trans_conf_value |= PIPECONF_ENABLE;
+       dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+
+       intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
+       intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+       intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
+                      trans_ddi_func_ctl_value);
+}
+
+void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+{
+       struct drm_dp_phy_test_params *data =
+               &intel_dp->compliance.test_data.phytest;
+       u8 link_status[DP_LINK_STATUS_SIZE];
+
+       if (!intel_dp_get_link_status(intel_dp, link_status)) {
+               DRM_DEBUG_KMS("failed to get link status\n");
+               return;
+       }
+
+       /* retrieve vswing & pre-emphasis setting */
+       intel_dp_get_adjust_train(intel_dp, link_status);
+
+       intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+       intel_dp_set_signal_levels(intel_dp);
+
+       intel_dp_phy_pattern_update(intel_dp);
+
+       intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+
+       drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
+                                   link_status[DP_DPCD_REV]);
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
-       u8 test_result = DP_TEST_NAK;
+       u8 test_result;
+
+       test_result = intel_dp_prepare_phytest(intel_dp);
+       if (test_result != DP_TEST_ACK)
+               DRM_ERROR("Phy test preparation failed\n");
+
+       intel_dp_process_phy_request(intel_dp);
+
        return test_result;
 }
 
@@ -5458,61 +5605,51 @@ static int
 intel_dp_check_mst_status(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-       bool bret;
+       bool need_retrain = false;
 
-       if (intel_dp->is_mst) {
-               u8 esi[DP_DPRX_ESI_LEN] = { 0 };
-               int ret = 0;
+       if (!intel_dp->is_mst)
+               return -EINVAL;
+
+       WARN_ON_ONCE(intel_dp->active_mst_links < 0);
+
+       for (;;) {
+               u8 esi[DP_DPRX_ESI_LEN] = {};
+               bool bret, handled;
                int retry;
-               bool handled;
 
-               WARN_ON_ONCE(intel_dp->active_mst_links < 0);
                bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
-go_again:
-               if (bret == true) {
-
-                       /* check link status - esi[10] = 0x200c */
-                       if (intel_dp->active_mst_links > 0 &&
-                           !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
-                               drm_dbg_kms(&i915->drm,
-                                           "channel EQ not ok, retraining\n");
-                               intel_dp_start_link_train(intel_dp);
-                               intel_dp_stop_link_train(intel_dp);
-                       }
+               if (!bret) {
+                       drm_dbg_kms(&i915->drm,
+                                   "failed to get ESI - device may have failed\n");
+                       return -EINVAL;
+               }
 
-                       drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
-                       ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
-
-                       if (handled) {
-                               for (retry = 0; retry < 3; retry++) {
-                                       int wret;
-                                       wret = drm_dp_dpcd_write(&intel_dp->aux,
-                                                                DP_SINK_COUNT_ESI+1,
-                                                                &esi[1], 3);
-                                       if (wret == 3) {
-                                               break;
-                                       }
-                               }
+               /* check link status - esi[10] = 0x200c */
+               if (intel_dp->active_mst_links > 0 && !need_retrain &&
+                   !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
+                       drm_dbg_kms(&i915->drm,
+                                   "channel EQ not ok, retraining\n");
+                       need_retrain = true;
+               }
 
-                               bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
-                               if (bret == true) {
-                                       drm_dbg_kms(&i915->drm,
-                                                   "got esi2 %3ph\n", esi);
-                                       goto go_again;
-                               }
-                       } else
-                               ret = 0;
+               drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
 
-                       return ret;
-               } else {
-                       drm_dbg_kms(&i915->drm,
-                                   "failed to get ESI - device may have failed\n");
-                       intel_dp->is_mst = false;
-                       drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
-                                                       intel_dp->is_mst);
+               drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+               if (!handled)
+                       break;
+
+               for (retry = 0; retry < 3; retry++) {
+                       int wret;
+
+                       wret = drm_dp_dpcd_write(&intel_dp->aux,
+                                                DP_SINK_COUNT_ESI+1,
+                                                &esi[1], 3);
+                       if (wret == 3)
+                               break;
                }
        }
-       return -EINVAL;
+
+       return need_retrain;
 }
 
 static bool
@@ -5549,20 +5686,102 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
        return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
 }
 
+static bool intel_dp_has_connector(struct intel_dp *intel_dp,
+                                  const struct drm_connector_state *conn_state)
+{
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+       struct intel_encoder *encoder;
+       enum pipe pipe;
+
+       if (!conn_state->best_encoder)
+               return false;
+
+       /* SST */
+       encoder = &dp_to_dig_port(intel_dp)->base;
+       if (conn_state->best_encoder == &encoder->base)
+               return true;
+
+       /* MST */
+       for_each_pipe(i915, pipe) {
+               encoder = &intel_dp->mst_encoders[pipe]->base;
+               if (conn_state->best_encoder == &encoder->base)
+                       return true;
+       }
+
+       return false;
+}
+
+static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
+                                     struct drm_modeset_acquire_ctx *ctx,
+                                     u32 *crtc_mask)
+{
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+       struct drm_connector_list_iter conn_iter;
+       struct intel_connector *connector;
+       int ret = 0;
+
+       *crtc_mask = 0;
+
+       if (!intel_dp_needs_link_retrain(intel_dp))
+               return 0;
+
+       drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+       for_each_intel_connector_iter(connector, &conn_iter) {
+               struct drm_connector_state *conn_state =
+                       connector->base.state;
+               struct intel_crtc_state *crtc_state;
+               struct intel_crtc *crtc;
+
+               if (!intel_dp_has_connector(intel_dp, conn_state))
+                       continue;
+
+               crtc = to_intel_crtc(conn_state->crtc);
+               if (!crtc)
+                       continue;
+
+               ret = drm_modeset_lock(&crtc->base.mutex, ctx);
+               if (ret)
+                       break;
+
+               crtc_state = to_intel_crtc_state(crtc->base.state);
+
+               drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
+
+               if (!crtc_state->hw.active)
+                       continue;
+
+               if (conn_state->commit &&
+                   !try_wait_for_completion(&conn_state->commit->hw_done))
+                       continue;
+
+               *crtc_mask |= drm_crtc_mask(&crtc->base);
+       }
+       drm_connector_list_iter_end(&conn_iter);
+
+       if (!intel_dp_needs_link_retrain(intel_dp))
+               *crtc_mask = 0;
+
+       return ret;
+}
+
+static bool intel_dp_is_connected(struct intel_dp *intel_dp)
+{
+       struct intel_connector *connector = intel_dp->attached_connector;
+
+       return connector->base.status == connector_status_connected ||
+               intel_dp->is_mst;
+}
+
 int intel_dp_retrain_link(struct intel_encoder *encoder,
                          struct drm_modeset_acquire_ctx *ctx)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-       struct intel_connector *connector = intel_dp->attached_connector;
-       struct drm_connector_state *conn_state;
-       struct intel_crtc_state *crtc_state;
        struct intel_crtc *crtc;
+       u32 crtc_mask;
        int ret;
 
-       /* FIXME handle the MST connectors as well */
-
-       if (!connector || connector->base.status != connector_status_connected)
+       if (!intel_dp_is_connected(intel_dp))
                return 0;
 
        ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
@@ -5570,46 +5789,42 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
        if (ret)
                return ret;
 
-       conn_state = connector->base.state;
-
-       crtc = to_intel_crtc(conn_state->crtc);
-       if (!crtc)
-               return 0;
-
-       ret = drm_modeset_lock(&crtc->base.mutex, ctx);
+       ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
        if (ret)
                return ret;
 
-       crtc_state = to_intel_crtc_state(crtc->base.state);
-
-       drm_WARN_ON(&dev_priv->drm, !intel_crtc_has_dp_encoder(crtc_state));
-
-       if (!crtc_state->hw.active)
+       if (crtc_mask == 0)
                return 0;
 
-       if (conn_state->commit &&
-           !try_wait_for_completion(&conn_state->commit->hw_done))
-               return 0;
+       drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
+                   encoder->base.base.id, encoder->base.name);
 
-       if (!intel_dp_needs_link_retrain(intel_dp))
-               return 0;
+       for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+               const struct intel_crtc_state *crtc_state =
+                       to_intel_crtc_state(crtc->base.state);
 
-       /* Suppress underruns caused by re-training */
-       intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
-       if (crtc_state->has_pch_encoder)
-               intel_set_pch_fifo_underrun_reporting(dev_priv,
-                                                     intel_crtc_pch_transcoder(crtc), false);
+               /* Suppress underruns caused by re-training */
+               intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
+               if (crtc_state->has_pch_encoder)
+                       intel_set_pch_fifo_underrun_reporting(dev_priv,
+                                                             intel_crtc_pch_transcoder(crtc), false);
+       }
 
        intel_dp_start_link_train(intel_dp);
        intel_dp_stop_link_train(intel_dp);
 
-       /* Keep underrun reporting disabled until things are stable */
-       intel_wait_for_vblank(dev_priv, crtc->pipe);
+       for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+               const struct intel_crtc_state *crtc_state =
+                       to_intel_crtc_state(crtc->base.state);
+
+               /* Keep underrun reporting disabled until things are stable */
+               intel_wait_for_vblank(dev_priv, crtc->pipe);
 
-       intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
-       if (crtc_state->has_pch_encoder)
-               intel_set_pch_fifo_underrun_reporting(dev_priv,
-                                                     intel_crtc_pch_transcoder(crtc), true);
+               intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
+               if (crtc_state->has_pch_encoder)
+                       intel_set_pch_fifo_underrun_reporting(dev_priv,
+                                                             intel_crtc_pch_transcoder(crtc), true);
+       }
 
        return 0;
 }
@@ -6280,8 +6495,6 @@ intel_dp_connector_register(struct drm_connector *connector)
        if (ret)
                return ret;
 
-       intel_connector_debugfs_add(connector);
-
        drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
                    intel_dp->aux.name, connector->kdev->kobj.name);
 
@@ -6662,9 +6875,9 @@ static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
          0, 0 },
 };
 
-static inline
-int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
-                                 u8 *rx_status)
+static int
+intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+                             u8 *rx_status)
 {
        struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
        ssize_t ret;
@@ -7253,7 +7466,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
        }
 
        if (intel_dp->is_mst) {
-               if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
+               switch (intel_dp_check_mst_status(intel_dp)) {
+               case -EINVAL:
                        /*
                         * If we were in MST mode, and device is not
                         * there, get out of MST mode
@@ -7267,6 +7481,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
                                                        intel_dp->is_mst);
 
                        return IRQ_NONE;
+               case 1:
+                       return IRQ_NONE;
+               default:
+                       break;
                }
        }
 
@@ -8299,6 +8517,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 
        intel_dig_port->dp.output_reg = output_reg;
        intel_dig_port->max_lanes = 4;
+       intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
+       intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
 
        intel_encoder->type = INTEL_OUTPUT_DP;
        intel_encoder->power_domain = intel_port_to_power_domain(port);