Merge tag 'drm-intel-next-2023-08-03' of git://anongit.freedesktop.org/drm/drm-intel...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / display / intel_dp.c

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da2..0367562 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -713,9 +713,18 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
 
                /*
                 * According to BSpec, 27 is the max DSC output bpp,
-                * 8 is the min DSC output bpp
+                * 8 is the min DSC output bpp.
+                * While we can still clamp higher bpp values to 27, saving bandwidth,
+                * if it is required to oompress up to bpp < 8, means we can't do
+                * that and probably means we can't fit the required mode, even with
+                * DSC enabled.
                 */
-               bits_per_pixel = clamp_t(u32, bits_per_pixel, 8, 27);
+               if (bits_per_pixel < 8) {
+                       drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
+                                   bits_per_pixel);
+                       return 0;
+               }
+               bits_per_pixel = min_t(u32, bits_per_pixel, 27);
        } else {
                /* Find the nearest match in the array of known BPPs from VESA */
                for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {