drm/i915/display: Eliminate IS_GEN9_{BC,LP}

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / display / intel_display_power.c

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 99126ca..9419ae8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -709,7 +709,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
         * BIOS's own request bits, which are forced-on for these power wells
         * when exiting DC5/6.
         */
-       if (IS_DISPLAY_VER(dev_priv, 9) && !IS_GEN9_LP(dev_priv) &&
+       if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
            (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
                val |= intel_de_read(dev_priv, regs->bios);
 
@@ -809,7 +809,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
                                          | DC_STATE_EN_DC9;
        else if (IS_DISPLAY_VER(dev_priv, 11))
                mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
-       else if (IS_GEN9_LP(dev_priv))
+       else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                mask |= DC_STATE_EN_DC9;
        else
                mask |= DC_STATE_EN_UPTO_DC6;
@@ -1060,7 +1060,7 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
        drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
 
        /* Wa Display #1183: skl,kbl,cfl */
-       if (IS_GEN9_BC(dev_priv))
+       if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
                intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
                               intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
 
@@ -1087,7 +1087,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
        drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
 
        /* Wa Display #1183: skl,kbl,cfl */
-       if (IS_GEN9_BC(dev_priv))
+       if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
                intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
                               intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
 
@@ -1189,7 +1189,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
 
        gen9_assert_dbuf_enabled(dev_priv);
 
-       if (IS_GEN9_LP(dev_priv))
+       if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                bxt_verify_ddi_phy_power_wells(dev_priv);
 
        if (DISPLAY_VER(dev_priv) >= 11)
@@ -4537,10 +4537,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
                max_dc = 3;
        else if (DISPLAY_VER(dev_priv) >= 12)
                max_dc = 4;
-       else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv) || IS_GEN9_BC(dev_priv))
-               max_dc = 2;
-       else if (IS_GEN9_LP(dev_priv))
+       else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                max_dc = 1;
+       else if (DISPLAY_VER(dev_priv) >= 9)
+               max_dc = 2;
        else
                max_dc = 0;
 
@@ -4549,7 +4549,8 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
         * not depending on the DMC firmware. It's needed by system
         * suspend/resume, so allow it unconditionally.
         */
-       mask = IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 11 ?
+       mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+               DISPLAY_VER(dev_priv) >= 11 ?
               DC_STATE_EN_DC9 : 0;
 
        if (!dev_priv->params.disable_power_well)
@@ -4692,7 +4693,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
                err = set_power_wells(power_domains, glk_power_wells);
        } else if (IS_BROXTON(dev_priv)) {
                err = set_power_wells(power_domains, bxt_power_wells);
-       } else if (IS_GEN9_BC(dev_priv)) {
+       } else if (IS_DISPLAY_VER(dev_priv, 9)) {
                err = set_power_wells(power_domains, skl_power_wells);
        } else if (IS_CHERRYVIEW(dev_priv)) {
                err = set_power_wells(power_domains, chv_power_wells);
@@ -5623,10 +5624,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
                icl_display_core_init(i915, resume);
        } else if (IS_CANNONLAKE(i915)) {
                cnl_display_core_init(i915, resume);
-       } else if (IS_GEN9_BC(i915)) {
-               skl_display_core_init(i915, resume);
-       } else if (IS_GEN9_LP(i915)) {
+       } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
                bxt_display_core_init(i915, resume);
+       } else if (IS_DISPLAY_VER(i915, 9)) {
+               skl_display_core_init(i915, resume);
        } else if (IS_CHERRYVIEW(i915)) {
                mutex_lock(&power_domains->lock);
                chv_phy_control_init(i915);
@@ -5784,10 +5785,10 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
                icl_display_core_uninit(i915);
        else if (IS_CANNONLAKE(i915))
                cnl_display_core_uninit(i915);
-       else if (IS_GEN9_BC(i915))
-               skl_display_core_uninit(i915);
-       else if (IS_GEN9_LP(i915))
+       else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
                bxt_display_core_uninit(i915);
+       else if (IS_DISPLAY_VER(i915, 9))
+               skl_display_core_uninit(i915);
 
        power_domains->display_core_suspended = true;
 }
@@ -5908,7 +5909,8 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
 
 void intel_display_power_suspend_late(struct drm_i915_private *i915)
 {
-       if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
+       if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
+           IS_BROXTON(i915)) {
                bxt_enable_dc9(i915);
                /* Tweaked Wa_14010685332:icp,jsp,mcc */
                if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
@@ -5921,7 +5923,8 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915)
 
 void intel_display_power_resume_early(struct drm_i915_private *i915)
 {
-       if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
+       if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
+           IS_BROXTON(i915)) {
                gen9_sanitize_dc_state(i915);
                bxt_disable_dc9(i915);
                /* Tweaked Wa_14010685332:icp,jsp,mcc */
@@ -5938,7 +5941,7 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
        if (DISPLAY_VER(i915) >= 11) {
                icl_display_core_uninit(i915);
                bxt_enable_dc9(i915);
-       } else if (IS_GEN9_LP(i915)) {
+       } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
                bxt_display_core_uninit(i915);
                bxt_enable_dc9(i915);
        } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
@@ -5959,7 +5962,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
                                 DC_STATE_EN_UPTO_DC5)
                                gen9_enable_dc5(i915);
                }
-       } else if (IS_GEN9_LP(i915)) {
+       } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
                bxt_disable_dc9(i915);
                bxt_display_core_init(i915, true);
                if (i915->csr.dmc_payload &&