drm/i915/dsi: Fix state mismatch warns for horizontal timings with DSC

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / display / intel_display_power.c

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6f9e792..0b3dd2a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2682,6 +2682,8 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        TGL_PW_2_POWER_DOMAINS |                        \
        BIT_ULL(POWER_DOMAIN_MODESET) |                 \
        BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
        BIT_ULL(POWER_DOMAIN_INIT))
 
 #define TGL_DDI_IO_D_TC1_POWER_DOMAINS (       \
@@ -4779,6 +4781,56 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
        intel_combo_phy_uninit(dev_priv);
 }
 
+struct buddy_page_mask {
+       u32 page_mask;
+       u8 type;
+       u8 num_channels;
+};
+
+static const struct buddy_page_mask tgl_buddy_page_masks[] = {
+       { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0xE },
+       { .num_channels = 1, .type = INTEL_DRAM_DDR4,   .page_mask = 0xF },
+       { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
+       { .num_channels = 2, .type = INTEL_DRAM_DDR4,   .page_mask = 0x1F },
+       {}
+};
+
+static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
+       { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
+       { .num_channels = 1, .type = INTEL_DRAM_DDR4,   .page_mask = 0x1 },
+       { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
+       { .num_channels = 2, .type = INTEL_DRAM_DDR4,   .page_mask = 0x3 },
+       {}
+};
+
+static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
+{
+       enum intel_dram_type type = dev_priv->dram_info.type;
+       u8 num_channels = dev_priv->dram_info.num_channels;
+       const struct buddy_page_mask *table;
+       int i;
+
+       if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+               /* Wa_1409767108: tgl */
+               table = wa_1409767108_buddy_page_masks;
+       else
+               table = tgl_buddy_page_masks;
+
+       for (i = 0; table[i].page_mask != 0; i++)
+               if (table[i].num_channels == num_channels &&
+                   table[i].type == type)
+                       break;
+
+       if (table[i].page_mask == 0) {
+               DRM_DEBUG_DRIVER("Unknown memory configuration; disabling address buddy logic.\n");
+               I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
+               I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
+       } else {
+               I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask);
+               I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask);
+       }
+}
+
 static void icl_display_core_init(struct drm_i915_private *dev_priv,
                                  bool resume)
 {
@@ -4811,6 +4863,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
        /* 6. Setup MBUS. */
        icl_mbus_init(dev_priv);
 
+       /* 7. Program arbiter BW_BUDDY registers */
+       if (INTEL_GEN(dev_priv) >= 12)
+               tgl_bw_buddy_init(dev_priv);
+
        if (resume && dev_priv->csr.dmc_payload)
                intel_csr_load_program(dev_priv);
 }
@@ -5013,6 +5069,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
 
        power_domains->initializing = true;
 
+       /* Must happen before power domain init on VLV/CHV */
+       intel_update_rawclk(i915);
+
        if (INTEL_GEN(i915) >= 11) {
                icl_display_core_init(i915, resume);
        } else if (IS_CANNONLAKE(i915)) {