Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.org/drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / display / intel_bw.c

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d7575aa..ba9e713 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -20,76 +20,9 @@ struct intel_qgv_point {
 struct intel_qgv_info {
        struct intel_qgv_point points[I915_NUM_QGV_POINTS];
        u8 num_points;
-       u8 num_channels;
        u8 t_bl;
-       enum intel_dram_type dram_type;
 };
 
-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
-                                         struct intel_qgv_info *qi)
-{
-       u32 val = 0;
-       int ret;
-
-       ret = sandybridge_pcode_read(dev_priv,
-                                    ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-                                    ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
-                                    &val, NULL);
-       if (ret)
-               return ret;
-
-       if (IS_GEN(dev_priv, 12)) {
-               switch (val & 0xf) {
-               case 0:
-                       qi->dram_type = INTEL_DRAM_DDR4;
-                       break;
-               case 3:
-                       qi->dram_type = INTEL_DRAM_LPDDR4;
-                       break;
-               case 4:
-                       qi->dram_type = INTEL_DRAM_DDR3;
-                       break;
-               case 5:
-                       qi->dram_type = INTEL_DRAM_LPDDR3;
-                       break;
-               default:
-                       MISSING_CASE(val & 0xf);
-                       break;
-               }
-       } else if (IS_GEN(dev_priv, 11)) {
-               switch (val & 0xf) {
-               case 0:
-                       qi->dram_type = INTEL_DRAM_DDR4;
-                       break;
-               case 1:
-                       qi->dram_type = INTEL_DRAM_DDR3;
-                       break;
-               case 2:
-                       qi->dram_type = INTEL_DRAM_LPDDR3;
-                       break;
-               case 3:
-                       qi->dram_type = INTEL_DRAM_LPDDR4;
-                       break;
-               default:
-                       MISSING_CASE(val & 0xf);
-                       break;
-               }
-       } else {
-               MISSING_CASE(INTEL_GEN(dev_priv));
-               qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
-       }
-
-       qi->num_channels = (val & 0xf0) >> 4;
-       qi->num_points = (val & 0xf00) >> 8;
-
-       if (IS_GEN(dev_priv, 12))
-               qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
-       else if (IS_GEN(dev_priv, 11))
-               qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
-
-       return 0;
-}
-
 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
                                         struct intel_qgv_point *sp,
                                         int point)
@@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
                              struct intel_qgv_info *qi)
 {
+       const struct dram_info *dram_info = &dev_priv->dram_info;
        int i, ret;
 
-       ret = icl_pcode_read_mem_global_info(dev_priv, qi);
-       if (ret)
-               return ret;
+       qi->num_points = dram_info->num_qgv_points;
+
+       if (IS_GEN(dev_priv, 12))
+               qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+       else if (IS_GEN(dev_priv, 11))
+               qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
 
        if (drm_WARN_ON(&dev_priv->drm,
                        qi->num_points > ARRAY_SIZE(qi->points)))
@@ -215,7 +152,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
 {
        struct intel_qgv_info qi = {};
        bool is_y_tile = true; /* assume y tile may be used */
-       int num_channels;
+       int num_channels = dev_priv->dram_info.num_channels;
        int deinterleave;
        int ipqdepth, ipqdepthpch;
        int dclk_max;
@@ -228,7 +165,6 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
                            "Failed to get memory subsystem information, ignoring bandwidth limits");
                return ret;
        }
-       num_channels = qi.num_channels;
 
        deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
        dclk_max = icl_sagv_max_dclk(&qi);