* OTHER DEALINGS IN THE SOFTWARE.
*/
+#define SWSMU_CODE_LAYER_L1
+
#include <linux/firmware.h>
#include <linux/pci.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_internal.h"
-#include "smu_v11_0.h"
-#include "smu_v12_0.h"
#include "atom.h"
#include "arcturus_ppt.h"
#include "navi10_ppt.h"
#include "sienna_cichlid_ppt.h"
#include "renoir_ppt.h"
+#include "amd_pcie.h"
/*
* DO NOT use these for err/warn/info/debug messages.
#undef pr_info
#undef pr_debug
-#undef __SMU_DUMMY_MAP
-#define __SMU_DUMMY_MAP(type) #type
-static const char* __smu_message_names[] = {
- SMU_MESSAGE_TYPES
-};
-
-const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
-{
- if (type < 0 || type >= SMU_MSG_MAX_COUNT)
- return "unknown smu message";
- return __smu_message_names[type];
-}
-
-#undef __SMU_DUMMY_MAP
-#define __SMU_DUMMY_MAP(fea) #fea
-static const char* __smu_feature_names[] = {
- SMU_FEATURE_MASKS
-};
-
-const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
-{
- if (feature < 0 || feature >= SMU_FEATURE_COUNT)
- return "unknown smu feature";
- return __smu_feature_names[feature];
-}
-
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
{
size_t size = 0;
- int ret = 0, i = 0;
- uint32_t feature_mask[2] = { 0 };
- int32_t feature_index = 0;
- uint32_t count = 0;
- uint32_t sort_feature[SMU_FEATURE_COUNT];
- uint64_t hw_feature_count = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
- if (ret)
- goto failed;
-
- size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
- feature_mask[1], feature_mask[0]);
+ size = smu_get_pp_feature_mask(smu, buf);
- for (i = 0; i < SMU_FEATURE_COUNT; i++) {
- feature_index = smu_feature_get_index(smu, i);
- if (feature_index < 0)
- continue;
- sort_feature[feature_index] = i;
- hw_feature_count++;
- }
-
- for (i = 0; i < hw_feature_count; i++) {
- size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
- count++,
- smu_get_feature_name(smu, sort_feature[i]),
- i,
- !!smu_feature_is_enabled(smu, sort_feature[i]) ?
- "enabled" : "disabled");
- }
-
-failed:
mutex_unlock(&smu->mutex);
return size;
}
-static int smu_feature_update_enable_state(struct smu_context *smu,
- uint64_t feature_mask,
- bool enabled)
-{
- struct smu_feature *feature = &smu->smu_feature;
- int ret = 0;
-
- if (enabled) {
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_EnableSmuFeaturesLow,
- lower_32_bits(feature_mask),
- NULL);
- if (ret)
- return ret;
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_EnableSmuFeaturesHigh,
- upper_32_bits(feature_mask),
- NULL);
- if (ret)
- return ret;
- } else {
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_DisableSmuFeaturesLow,
- lower_32_bits(feature_mask),
- NULL);
- if (ret)
- return ret;
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_DisableSmuFeaturesHigh,
- upper_32_bits(feature_mask),
- NULL);
- if (ret)
- return ret;
- }
-
- mutex_lock(&feature->mutex);
- if (enabled)
- bitmap_or(feature->enabled, feature->enabled,
- (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
- else
- bitmap_andnot(feature->enabled, feature->enabled,
- (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
- mutex_unlock(&feature->mutex);
-
- return ret;
-}
-
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
{
int ret = 0;
- uint32_t feature_mask[2] = { 0 };
- uint64_t feature_2_enabled = 0;
- uint64_t feature_2_disabled = 0;
- uint64_t feature_enables = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
- if (ret)
- goto out;
-
- feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
-
- feature_2_enabled = ~feature_enables & new_mask;
- feature_2_disabled = feature_enables & ~new_mask;
-
- if (feature_2_enabled) {
- ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
- if (ret)
- goto out;
- }
- if (feature_2_disabled) {
- ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
- if (ret)
- goto out;
- }
+ ret = smu_set_pp_feature_mask(smu, new_mask);
-out:
mutex_unlock(&smu->mutex);
return ret;
}
-int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
+int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
{
int ret = 0;
+ struct smu_context *smu = &adev->smu;
- if (!if_version && !smu_version)
- return -EINVAL;
-
- if (smu->smc_fw_if_version && smu->smc_fw_version)
- {
- if (if_version)
- *if_version = smu->smc_fw_if_version;
-
- if (smu_version)
- *smu_version = smu->smc_fw_version;
-
- return 0;
- }
-
- if (if_version) {
- ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
- if (ret)
- return ret;
-
- smu->smc_fw_if_version = *if_version;
- }
-
- if (smu_version) {
- ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
- if (ret)
- return ret;
-
- smu->smc_fw_version = *smu_version;
- }
+ if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
+ *value = smu_get_gfx_off_status(smu);
+ else
+ ret = -EINVAL;
return ret;
}
-int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t min, uint32_t max, bool lock_needed)
+int smu_set_soft_freq_range(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t min,
+ uint32_t max)
{
int ret = 0;
- if (!smu_clk_dpm_is_enabled(smu, clk_type))
- return 0;
-
- if (lock_needed)
- mutex_lock(&smu->mutex);
- ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
- if (lock_needed)
- mutex_unlock(&smu->mutex);
-
- return ret;
-}
-
-int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t min, uint32_t max)
-{
- int ret = 0, clk_id = 0;
- uint32_t param;
-
- if (min <= 0 && max <= 0)
- return -EINVAL;
-
- if (!smu_clk_dpm_is_enabled(smu, clk_type))
- return 0;
-
- clk_id = smu_clk_get_index(smu, clk_type);
- if (clk_id < 0)
- return clk_id;
-
- if (max > 0) {
- param = (uint32_t)((clk_id << 16) | (max & 0xffff));
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
- param, NULL);
- if (ret)
- return ret;
- }
+ mutex_lock(&smu->mutex);
- if (min > 0) {
- param = (uint32_t)((clk_id << 16) | (min & 0xffff));
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
- param, NULL);
- if (ret)
- return ret;
- }
+ if (smu->ppt_funcs->set_soft_freq_limited_range)
+ ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
+ clk_type,
+ min,
+ max);
+ mutex_unlock(&smu->mutex);
return ret;
}
-int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max, bool lock_needed)
+int smu_get_dpm_freq_range(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *min,
+ uint32_t *max)
{
- uint32_t clock_limit;
int ret = 0;
if (!min && !max)
return -EINVAL;
- if (lock_needed)
- mutex_lock(&smu->mutex);
-
- if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- clock_limit = smu->smu_table.boot_values.uclk;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- clock_limit = smu->smu_table.boot_values.gfxclk;
- break;
- case SMU_SOCCLK:
- clock_limit = smu->smu_table.boot_values.socclk;
- break;
- default:
- clock_limit = 0;
- break;
- }
+ mutex_lock(&smu->mutex);
- /* clock in Mhz unit */
- if (min)
- *min = clock_limit / 100;
- if (max)
- *max = clock_limit / 100;
- } else {
- /*
- * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
- * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
- */
- ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
- }
+ if (smu->ppt_funcs->get_dpm_ultimate_freq)
+ ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
+ clk_type,
+ min,
+ max);
- if (lock_needed)
- mutex_unlock(&smu->mutex);
+ mutex_unlock(&smu->mutex);
return ret;
}
-int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
- uint16_t level, uint32_t *value)
+static int smu_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable)
{
- int ret = 0, clk_id = 0;
- uint32_t param;
-
- if (!value)
- return -EINVAL;
+ struct smu_power_context *smu_power = &smu->smu_power;
+ struct smu_power_gate *power_gate = &smu_power->power_gate;
+ int ret = 0;
- if (!smu_clk_dpm_is_enabled(smu, clk_type))
+ if (!smu->ppt_funcs->dpm_set_vcn_enable)
return 0;
- clk_id = smu_clk_get_index(smu, clk_type);
- if (clk_id < 0)
- return clk_id;
+ mutex_lock(&power_gate->vcn_gate_lock);
- param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
+ if (atomic_read(&power_gate->vcn_gated) ^ enable)
+ goto out;
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmFreqByIndex,
- param, value);
- if (ret)
- return ret;
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+ if (!ret)
+ atomic_set(&power_gate->vcn_gated, !enable);
- /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
- * now, we un-support it */
- *value = *value & 0x7fffffff;
+out:
+ mutex_unlock(&power_gate->vcn_gate_lock);
return ret;
}
-int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *value)
-{
- return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
-}
-
-int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min_value, uint32_t *max_value)
+static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
+ bool enable)
{
+ struct smu_power_context *smu_power = &smu->smu_power;
+ struct smu_power_gate *power_gate = &smu_power->power_gate;
int ret = 0;
- uint32_t level_count = 0;
-
- if (!min_value && !max_value)
- return -EINVAL;
-
- if (min_value) {
- /* by default, level 0 clock value as min value */
- ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
- if (ret)
- return ret;
- }
-
- if (max_value) {
- ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
- if (ret)
- return ret;
- ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
- if (ret)
- return ret;
- }
+ if (!smu->ppt_funcs->dpm_set_jpeg_enable)
+ return 0;
- return ret;
-}
+ mutex_lock(&power_gate->jpeg_gate_lock);
-bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
-{
- enum smu_feature_mask feature_id = 0;
+ if (atomic_read(&power_gate->jpeg_gated) ^ enable)
+ goto out;
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- feature_id = SMU_FEATURE_DPM_UCLK_BIT;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
- break;
- case SMU_SOCCLK:
- feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
- break;
- default:
- return true;
- }
+ ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
+ if (!ret)
+ atomic_set(&power_gate->jpeg_gated, !enable);
- if(!smu_feature_is_enabled(smu, feature_id)) {
- return false;
- }
+out:
+ mutex_unlock(&power_gate->jpeg_gate_lock);
- return true;
+ return ret;
}
/**
return -EOPNOTSUPP;
switch (block_type) {
+ /*
+ * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
+ * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
+ */
case AMD_IP_BLOCK_TYPE_UVD:
- ret = smu_dpm_set_uvd_enable(smu, !gate);
+ case AMD_IP_BLOCK_TYPE_VCN:
+ ret = smu_dpm_set_vcn_enable(smu, !gate);
if (ret)
- dev_err(smu->adev->dev, "Failed to power %s UVD!\n",
+ dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
gate ? "gate" : "ungate");
break;
- case AMD_IP_BLOCK_TYPE_VCE:
- ret = smu_dpm_set_vce_enable(smu, !gate);
- break;
case AMD_IP_BLOCK_TYPE_GFX:
ret = smu_gfx_off_control(smu, gate);
if (ret)
gate ? "gate" : "ungate");
break;
default:
- break;
+ dev_err(smu->adev->dev, "Unsupported block type!\n");
+ return -EINVAL;
}
return ret;
return 0;
}
-int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
- void *data, uint32_t *size)
-{
- struct smu_power_context *smu_power = &smu->smu_power;
- struct smu_power_gate *power_gate = &smu_power->power_gate;
- int ret = 0;
-
- if(!data || !size)
- return -EINVAL;
-
- switch (sensor) {
- case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
- *((uint32_t *)data) = smu->pstate_sclk;
- *size = 4;
- break;
- case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
- *((uint32_t *)data) = smu->pstate_mclk;
- *size = 4;
- break;
- case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
- ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
- *size = 8;
- break;
- case AMDGPU_PP_SENSOR_UVD_POWER:
- *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
- *size = 4;
- break;
- case AMDGPU_PP_SENSOR_VCE_POWER:
- *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
- *size = 4;
- break;
- case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
- *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
- *size = 4;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- if (ret)
- *size = 0;
-
- return ret;
-}
-
-int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
- void *table_data, bool drv2smu)
-{
- struct smu_table_context *smu_table = &smu->smu_table;
- struct amdgpu_device *adev = smu->adev;
- struct smu_table *table = &smu_table->driver_table;
- int table_id = smu_table_get_index(smu, table_index);
- uint32_t table_size;
- int ret = 0;
- if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
- return -EINVAL;
-
- table_size = smu_table->tables[table_index].size;
-
- if (drv2smu) {
- memcpy(table->cpu_addr, table_data, table_size);
- /*
- * Flush hdp cache: to guard the content seen by
- * GPU is consitent with CPU.
- */
- amdgpu_asic_flush_hdp(adev, NULL);
- }
-
- ret = smu_send_smc_msg_with_param(smu, drv2smu ?
- SMU_MSG_TransferTableDram2Smu :
- SMU_MSG_TransferTableSmu2Dram,
- table_id | ((argument & 0xFFFF) << 16),
- NULL);
- if (ret)
- return ret;
-
- if (!drv2smu) {
- amdgpu_asic_flush_hdp(adev, NULL);
- memcpy(table_data, table->cpu_addr, table_size);
- }
-
- return ret;
-}
-
bool is_support_sw_smu(struct amdgpu_device *adev)
{
if (adev->asic_type >= CHIP_ARCTURUS)
return ret;
}
-int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
-{
- struct smu_feature *feature = &smu->smu_feature;
- int feature_id;
- int ret = 0;
-
- if (smu->is_apu)
- return 1;
- feature_id = smu_feature_get_index(smu, mask);
- if (feature_id < 0)
- return 0;
-
- WARN_ON(feature_id > feature->feature_num);
-
- mutex_lock(&feature->mutex);
- ret = test_bit(feature_id, feature->enabled);
- mutex_unlock(&feature->mutex);
-
- return ret;
-}
-
-int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
- bool enable)
-{
- struct smu_feature *feature = &smu->smu_feature;
- int feature_id;
-
- feature_id = smu_feature_get_index(smu, mask);
- if (feature_id < 0)
- return -EINVAL;
-
- WARN_ON(feature_id > feature->feature_num);
-
- return smu_feature_update_enable_state(smu,
- 1ULL << feature_id,
- enable);
-}
-
-int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
-{
- struct smu_feature *feature = &smu->smu_feature;
- int feature_id;
- int ret = 0;
-
- feature_id = smu_feature_get_index(smu, mask);
- if (feature_id < 0)
- return 0;
-
- WARN_ON(feature_id > feature->feature_num);
-
- mutex_lock(&feature->mutex);
- ret = test_bit(feature_id, feature->supported);
- mutex_unlock(&feature->mutex);
-
- return ret;
-}
-
static int smu_set_funcs(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
smu->od_enabled =false;
break;
case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
sienna_cichlid_set_ppt_funcs(smu);
break;
case CHIP_RENOIR:
* gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
* type of clks.
*/
- ret = smu_populate_smc_tables(smu);
+ ret = smu_set_default_dpm_table(smu);
if (ret) {
dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
return ret;
}
- ret = smu_init_max_sustainable_clocks(smu);
- if (ret) {
- dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
- return ret;
- }
-
ret = smu_populate_umd_state_clk(smu);
if (ret) {
dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
return ret;
}
- ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
+ ret = smu_get_asic_power_limits(smu);
if (ret) {
- dev_err(adev->dev, "Failed to get default power limit!\n");
+ dev_err(adev->dev, "Failed to get asic power limits!\n");
return ret;
}
return 0;
}
-int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
- uint16_t *size, uint8_t *frev, uint8_t *crev,
- uint8_t **addr)
-{
- struct amdgpu_device *adev = smu->adev;
- uint16_t data_start;
-
- if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
- size, frev, crev, &data_start))
- return -EINVAL;
-
- *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
-
- return 0;
-}
-
static int smu_init_fb_allocations(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
if (ret)
return ret;
+ ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
+ if (ret)
+ return ret;
+
return 0;
}
{
int ret;
+ smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
+
ret = smu_free_memory_pool(smu);
if (ret)
return ret;
mutex_init(&smu->message_lock);
INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
+ atomic64_set(&smu->throttle_int_counter, 0);
smu->watermarks_bitmap = 0;
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+ atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
+ atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
+ mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
+ mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
+
smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
return 0;
}
+static int smu_get_thermal_temperature_range(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ struct smu_temperature_range *range =
+ &smu->thermal_range;
+ int ret = 0;
+
+ if (!smu->ppt_funcs->get_thermal_temperature_range)
+ return 0;
+
+ ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
+ if (ret)
+ return ret;
+
+ adev->pm.dpm.thermal.min_temp = range->min;
+ adev->pm.dpm.thermal.max_temp = range->max;
+ adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
+ adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
+ adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
+ adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
+ adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
+ adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
+ adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
+
+ return ret;
+}
+
static int smu_smc_hw_setup(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
+ uint32_t pcie_gen = 0, pcie_width = 0;
int ret;
- if (smu_is_dpm_running(smu) && adev->in_suspend) {
+ if (adev->in_suspend && smu_is_dpm_running(smu)) {
dev_info(adev->dev, "dpm has been enabled\n");
return 0;
}
if (!smu_is_dpm_running(smu))
dev_info(adev->dev, "dpm has been disabled\n");
- ret = smu_override_pcie_parameters(smu);
- if (ret)
+ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+ pcie_gen = 3;
+ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+ pcie_gen = 2;
+ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+ pcie_gen = 1;
+ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+ pcie_gen = 0;
+
+ /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
+ * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
+ * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
+ */
+ if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+ pcie_width = 6;
+ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+ pcie_width = 5;
+ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+ pcie_width = 4;
+ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+ pcie_width = 3;
+ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+ pcie_width = 2;
+ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+ pcie_width = 1;
+ ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
+ if (ret) {
+ dev_err(adev->dev, "Attempt to override pcie params failed!\n");
return ret;
+ }
- ret = smu_enable_thermal_alert(smu);
+ ret = smu_get_thermal_temperature_range(smu);
if (ret) {
- dev_err(adev->dev, "Failed to enable thermal alert!\n");
+ dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
return ret;
}
- ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
- if (ret)
+ ret = smu_enable_thermal_alert(smu);
+ if (ret) {
+ dev_err(adev->dev, "Failed to enable thermal alert!\n");
return ret;
+ }
ret = smu_disable_umc_cdr_12gbps_workaround(smu);
if (ret) {
* Set min deep sleep dce fclk with bootup value from vbios via
* SetMinDeepSleepDcefclk MSG.
*/
- ret = smu_set_min_dcef_deep_sleep(smu);
+ ret = smu_set_min_dcef_deep_sleep(smu,
+ smu->smu_table.boot_values.dcefclk / 100);
if (ret)
return ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
+ smu->pm_enabled = false;
return 0;
+ }
ret = smu_start_smc_engine(smu);
if (ret) {
if (smu->is_apu) {
smu_powergate_sdma(&adev->smu, false);
- smu_powergate_vcn(&adev->smu, false);
- smu_powergate_jpeg(&adev->smu, false);
+ smu_dpm_set_vcn_enable(smu, true);
+ smu_dpm_set_jpeg_enable(smu, true);
smu_set_gfx_cgpg(&adev->smu, true);
}
return ret;
}
+ /*
+ * Move maximum sustainable clock retrieving here considering
+ * 1. It is not needed on resume(from S3).
+ * 2. DAL settings come between .hw_init and .late_init of SMU.
+ * And DAL needs to know the maximum sustainable clocks. Thus
+ * it cannot be put in .late_init().
+ */
+ ret = smu_init_max_sustainable_clocks(smu);
+ if (ret) {
+ dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
+ return ret;
+ }
+
adev->pm.dpm_enabled = true;
dev_info(adev->dev, "SMU is initialized successfully!\n");
static int smu_disable_dpms(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- uint64_t features_to_disable;
int ret = 0;
bool use_baco = !smu->is_apu &&
- ((adev->in_gpu_reset &&
+ ((amdgpu_in_reset(adev) &&
(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
* BACO feature has to be kept enabled.
*/
if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
- features_to_disable = U64_MAX &
- ~(1ULL << smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT));
- ret = smu_feature_update_enable_state(smu,
- features_to_disable,
- 0);
+ ret = smu_disable_all_features_with_exception(smu,
+ SMU_FEATURE_BACO_BIT);
if (ret)
dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
} else {
struct amdgpu_device *adev = smu->adev;
int ret = 0;
- smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
-
cancel_work_sync(&smu->throttling_logging_work);
ret = smu_disable_thermal_alert(smu);
if (smu->is_apu) {
smu_powergate_sdma(&adev->smu, true);
- smu_powergate_vcn(&adev->smu, true);
- smu_powergate_jpeg(&adev->smu, true);
+ smu_dpm_set_vcn_enable(smu, false);
+ smu_dpm_set_jpeg_enable(smu, false);
}
if (!smu->pm_enabled)
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->set_deep_sleep_dcefclk)
- smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
- display_config->min_dcef_deep_sleep_set_clk / 100);
+ smu_set_min_dcef_deep_sleep(smu,
+ display_config->min_dcef_deep_sleep_set_clk / 100);
for (index = 0; index < display_config->num_path_including_non_display; index++) {
if (display_config->displays[index].controller_id != 0)
return 0;
}
-int smu_adjust_power_state_dynamic(struct smu_context *smu,
+static int smu_adjust_power_state_dynamic(struct smu_context *smu,
enum amd_dpm_forced_level level,
bool skip_display_settings)
{
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask,
- bool lock_needed)
+ uint32_t mask)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
return -EINVAL;
}
- if (lock_needed)
- mutex_lock(&smu->mutex);
+ mutex_lock(&smu->mutex);
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
- if (lock_needed)
- mutex_unlock(&smu->mutex);
+ mutex_unlock(&smu->mutex);
return ret;
}
return 0;
}
- /* some asics may not support those messages */
- if (smu_msg_get_index(smu, msg) < 0) {
- mutex_unlock(&smu->mutex);
- return 0;
- }
-
ret = smu_send_smc_msg(smu, msg, NULL);
+ /* some asics may not support those messages */
+ if (ret == -EINVAL)
+ ret = 0;
if (ret)
dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
int smu_write_watermarks_table(struct smu_context *smu)
{
- void *watermarks_table = smu->smu_table.watermarks_table;
+ int ret = 0;
- if (!watermarks_table)
- return -EINVAL;
+ if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+ return -EOPNOTSUPP;
- return smu_update_table(smu,
- SMU_TABLE_WATERMARKS,
- 0,
- watermarks_table,
- true);
+ mutex_lock(&smu->mutex);
+
+ ret = smu_set_watermarks_table(smu, NULL);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
}
int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
{
- void *table = smu->smu_table.watermarks_table;
+ int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
- if (!table)
- return -EINVAL;
-
mutex_lock(&smu->mutex);
if (!smu->disable_watermark &&
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
- smu_set_watermarks_table(smu, table, clock_ranges);
+ ret = smu_set_watermarks_table(smu, clock_ranges);
if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
smu->watermarks_bitmap |= WATERMARKS_EXIST;
mutex_unlock(&smu->mutex);
- return 0;
+ return ret;
}
int smu_set_ac_dc(struct smu_context *smu)
int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
- bool def,
- bool lock_needed)
+ bool max_setting)
{
- int ret = 0;
-
- if (lock_needed) {
- if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
- return -EOPNOTSUPP;
+ if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+ return -EOPNOTSUPP;
- mutex_lock(&smu->mutex);
- }
+ mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->get_power_limit)
- ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
+ *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
- if (lock_needed)
- mutex_unlock(&smu->mutex);
+ mutex_unlock(&smu->mutex);
- return ret;
+ return 0;
}
int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
mutex_lock(&smu->mutex);
+ if (limit > smu->max_power_limit) {
+ dev_err(smu->adev->dev,
+ "New power limit (%d) is over the max allowed %d\n",
+ limit, smu->max_power_limit);
+ goto out;
+ }
+
+ if (!limit)
+ limit = smu->current_power_limit;
+
if (smu->ppt_funcs->set_power_limit)
ret = smu->ppt_funcs->set_power_limit(smu, limit);
+out:
mutex_unlock(&smu->mutex);
return ret;
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->od_edit_dpm_table)
+ if (smu->ppt_funcs->od_edit_dpm_table) {
ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
+ if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
+ ret = smu_handle_task(smu,
+ smu->smu_dpm.dpm_level,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
+ }
mutex_unlock(&smu->mutex);
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
+ if (!data || !size)
+ return -EINVAL;
+
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->read_sensor)
- ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
+ if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
+ goto unlock;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
+ *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
+ *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+ ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
+ *size = 8;
+ break;
+ case AMDGPU_PP_SENSOR_UVD_POWER:
+ *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_VCE_POWER:
+ *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
+ *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
+ *(uint32_t *)data = 0;
+ *size = 4;
+ break;
+ default:
+ *size = 0;
+ ret = -EOPNOTSUPP;
+ break;
+ }
+unlock:
mutex_unlock(&smu->mutex);
return ret;
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->set_deep_sleep_dcefclk)
- ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
+ ret = smu_set_min_dcef_deep_sleep(smu, clk);
mutex_unlock(&smu->mutex);
return ret;
}
+bool smu_mode1_reset_is_support(struct smu_context *smu)
+{
+ bool ret = false;
+
+ if (!smu->pm_enabled)
+ return false;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
+ ret = smu->ppt_funcs->mode1_reset_is_support(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_mode1_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if (!smu->pm_enabled)
+ return -EOPNOTSUPP;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->mode1_reset)
+ ret = smu->ppt_funcs->mode1_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
int smu_mode2_reset(struct smu_context *smu)
{
int ret = 0;
return ret;
}
-uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
+ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
+ void **table)
{
- uint32_t ret = 0;
+ ssize_t size;
- if (smu->ppt_funcs->get_pptable_power_limit)
- ret = smu->ppt_funcs->get_pptable_power_limit(smu);
+ if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+ return -EOPNOTSUPP;
- return ret;
-}
+ if (!smu->ppt_funcs->get_gpu_metrics)
+ return -EOPNOTSUPP;
-int smu_powergate_vcn(struct smu_context *smu, bool gate)
-{
- if (!smu->is_apu)
- return 0;
+ mutex_lock(&smu->mutex);
- return smu_dpm_set_uvd_enable(smu, !gate);
-}
+ size = smu->ppt_funcs->get_gpu_metrics(smu, table);
-int smu_powergate_jpeg(struct smu_context *smu, bool gate)
-{
- if (!smu->is_apu)
- return 0;
+ mutex_unlock(&smu->mutex);
- return smu_dpm_set_jpeg_enable(smu, !gate);
+ return size;
}
projects / linux-2.6-microblaze.git / blobdiff