drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register address

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / smu_v11_0.c

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index cf6176a..a621185 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -78,6 +78,9 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
 
+#define mmTHM_BACO_CNTL_ARCT                   0xA7
+#define mmTHM_BACO_CNTL_ARCT_BASE_IDX          0
+
 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
 static int link_speed[] = {25, 50, 80, 160};
 
@@ -474,12 +477,14 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 int smu_v11_0_init_power(struct smu_context *smu)
 {
        struct smu_power_context *smu_power = &smu->smu_power;
+       size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
+                       sizeof(struct smu_11_5_power_context) :
+                       sizeof(struct smu_11_0_power_context);
 
-       smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context),
-                                          GFP_KERNEL);
+       smu_power->power_context = kzalloc(size, GFP_KERNEL);
        if (!smu_power->power_context)
                return -ENOMEM;
-       smu_power->power_context_size = sizeof(struct smu_11_0_power_context);
+       smu_power->power_context_size = size;
 
        return 0;
 }
@@ -1530,9 +1535,15 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
                        break;
                default:
                        if (!ras || !ras->supported) {
-                               data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
-                               data |= 0x80000000;
-                               WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+                               if (adev->asic_type == CHIP_ARCTURUS) {
+                                       data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
+                                       data |= 0x80000000;
+                                       WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
+                               } else {
+                                       data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+                                       data |= 0x80000000;
+                                       WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+                               }
 
                                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
                        } else {
@@ -2021,30 +2032,6 @@ int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
        return link_speed[speed_level];
 }
 
-void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
-{
-       memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
-
-       gpu_metrics->common_header.structure_size =
-                               sizeof(struct gpu_metrics_v1_0);
-       gpu_metrics->common_header.format_revision = 1;
-       gpu_metrics->common_header.content_revision = 0;
-
-       gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
-}
-
-void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
-{
-       memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
-
-       gpu_metrics->common_header.structure_size =
-                               sizeof(struct gpu_metrics_v2_0);
-       gpu_metrics->common_header.format_revision = 2;
-       gpu_metrics->common_header.content_revision = 0;
-
-       gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
-}
-
 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
                              bool enablement)
 {