drm/amd/display: Fix dpstreamclk programming

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn31 / dcn31_dccg.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 269cabb..0902ce5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -28,10 +28,6 @@
 
 #include "dcn30/dcn30_dccg.h"
 
-#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
-       .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
-
-
 #define DCCG_REG_LIST_DCN31() \
        SR(DPPCLK_DTO_CTRL),\
        DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
@@ -124,6 +120,10 @@
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
+       DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+       DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+       DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+       DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
        DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
@@ -161,11 +161,6 @@ struct dccg *dccg31_create(
 
 void dccg31_init(struct dccg *dccg);
 
-void dccg31_set_dpstreamclk(
-               struct dccg *dccg,
-               enum hdmistreamclk_source src,
-               int otg_inst);
-
 void dccg31_enable_symclk32_se(
                struct dccg *dccg,
                int hpo_se_inst,
@@ -192,10 +187,42 @@ void dccg31_set_physymclk(
 
 void dccg31_set_audio_dtbclk_dto(
                struct dccg *dccg,
-               uint32_t req_audio_dtbclk_khz);
+               const struct dtbclk_dto_params *params);
+
+void dccg31_update_dpp_dto(
+       struct dccg *dccg,
+       int dpp_inst,
+       int req_dppclk);
+
+void dccg31_get_dccg_ref_freq(
+       struct dccg *dccg,
+       unsigned int xtalin_freq_inKhz,
+       unsigned int *dccg_ref_freq_inKhz);
 
-void dccg31_set_hdmistreamclk(
+void dccg31_set_dpstreamclk(
+       struct dccg *dccg,
+       enum streamclk_source src,
+       int otg_inst,
+       int dp_hpo_inst);
+
+void dccg31_set_dtbclk_dto(
                struct dccg *dccg,
-               enum hdmistreamclk_source src);
+               const struct dtbclk_dto_params *params);
+
+void dccg31_otg_add_pixel(
+       struct dccg *dccg,
+       uint32_t otg_inst);
+
+void dccg31_otg_drop_pixel(
+       struct dccg *dccg,
+       uint32_t otg_inst);
+
+void dccg31_set_dispclk_change_mode(
+       struct dccg *dccg,
+       enum dentist_dispclk_change_mode change_mode);
+
+void dccg31_disable_dscclk(struct dccg *dccg, int inst);
+
+void dccg31_enable_dscclk(struct dccg *dccg, int inst);
 
 #endif //__DCN31_DCCG_H__