drm/amd/display: Undo ODM combine

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn30 / dcn30_resource.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index e50c695..602ec9a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -816,7 +816,7 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = true,
                        .nv12 = true,
                        .fp16 = true,
-                       .p010 = false,
+                       .p010 = true,
                        .ayuv = false,
        },
 
@@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .timing_trace = false,
        .clock_trace = true,
        .disable_pplib_clock_request = true,
-       .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+       .pipe_split_policy = MPC_SPLIT_DYNAMIC,
        .force_single_disp_pipe_split = false,
        .disable_dcc = DCC_ENABLE,
        .vsr_support = true,
@@ -875,7 +875,7 @@ static const struct dc_debug_options debug_defaults_diags = {
        .use_max_lb = true
 };
 
-void dcn30_dpp_destroy(struct dpp **dpp)
+static void dcn30_dpp_destroy(struct dpp **dpp)
 {
        kfree(TO_DCN20_DPP(*dpp));
        *dpp = NULL;
@@ -992,7 +992,7 @@ static struct mpc *dcn30_mpc_create(
        return &mpc30->base;
 }
 
-struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
+static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
 {
        int i;
 
@@ -1143,9 +1143,8 @@ static struct afmt *dcn30_afmt_create(
        return &afmt3->base;
 }
 
-struct stream_encoder *dcn30_stream_encoder_create(
-       enum engine_id eng_id,
-       struct dc_context *ctx)
+static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
+                                                         struct dc_context *ctx)
 {
        struct dcn10_stream_encoder *enc1;
        struct vpg *vpg;
@@ -1179,8 +1178,7 @@ struct stream_encoder *dcn30_stream_encoder_create(
        return &enc1->base;
 }
 
-struct dce_hwseq *dcn30_hwseq_create(
-       struct dc_context *ctx)
+static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
 {
        struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 
@@ -2128,10 +2126,10 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
                int pipe_cnt,
                int vlevel)
 {
+       int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
        int i, pipe_idx;
-       double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
-       bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
-                       dm_dram_clock_change_unsupported;
+       double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
+       bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
 
        if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
                dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
@@ -2207,6 +2205,7 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
                context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
                context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
        }
+
        context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
@@ -2638,6 +2637,8 @@ static bool dcn30_resource_construct(
        dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
        dc->caps.color.mpc.ocsc = 1;
 
+       dc->caps.hdmi_frl_pcon_support = true;
+
        /* read VBIOS LTTPR caps */
        {
                if (ctx->dc_bios->funcs->get_lttpr_caps) {