drm/amd/display: Update register defines

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_mmhubbub.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
index 3fccd5e..7bcee58 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
@@ -36,26 +36,6 @@
 #define BASE(seg) \
        BASE_INNER(seg)
 
-#define SR(reg_name)\
-               .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-                                       mm ## reg_name
-
-#define SRI(reg_name, block, id)\
-       .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-                                       mm ## block ## id ## _ ## reg_name
-
-#define SRI2(reg_name, block, id)\
-       .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
-                                       mm ## reg_name
-
-#define SRII(reg_name, block, id)\
-       .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-                                       mm ## block ## id ## _ ## reg_name
-
-#define SF(reg_name, field_name, post_fix)\
-       .field_name = reg_name ## __ ## field_name ## post_fix
-
-
 #define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \
        SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
        SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\