drm/amd/display: Add dependant changes for DCN32/321

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_stream_encoder.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 293595a..02c7707 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -73,6 +73,7 @@
        SRI(HDMI_ACR_48_1, DIG, id),\
        SRI(DP_DB_CNTL, DP, id), \
        SRI(DP_MSA_MISC, DP, id), \
+       SRI(DP_MSA_VBID_MISC, DP, id), \
        SRI(DP_MSA_COLORIMETRY, DP, id), \
        SRI(DP_MSA_TIMING_PARAM1, DP, id), \
        SRI(DP_MSA_TIMING_PARAM2, DP, id), \
@@ -186,6 +187,7 @@ struct dcn10_stream_enc_registers {
        uint32_t HDMI_GENERIC_PACKET_CONTROL9;
        uint32_t HDMI_GENERIC_PACKET_CONTROL10;
        uint32_t DIG_CLOCK_PATTERN;
+       uint32_t DIG_FIFO_CTRL0;
 };
 
 
@@ -337,8 +339,14 @@ struct dcn10_stream_enc_registers {
        SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
        SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
 
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
+       SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh),\
+       SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)
+#else
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
        SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
+#endif
 
 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
        SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
@@ -567,16 +575,33 @@ struct dcn10_stream_enc_registers {
        type DP_SEC_GSP11_ENABLE;\
        type DP_SEC_GSP11_LINE_NUM
 
+#define SE_REG_FIELD_LIST_DCN3_2(type) \
+       type DIG_SYMCLK_FE_ON;\
+       type DIG_FIFO_READ_START_LEVEL;\
+       type DIG_FIFO_ENABLE;\
+       type DIG_FIFO_RESET;\
+       type DIG_FIFO_RESET_DONE
+
 struct dcn10_stream_encoder_shift {
        SE_REG_FIELD_LIST_DCN1_0(uint8_t);
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+       uint8_t HDMI_ACP_SEND;
+#endif
        SE_REG_FIELD_LIST_DCN2_0(uint8_t);
        SE_REG_FIELD_LIST_DCN3_0(uint8_t);
+       SE_REG_FIELD_LIST_DCN3_2(uint8_t);
+
 };
 
 struct dcn10_stream_encoder_mask {
        SE_REG_FIELD_LIST_DCN1_0(uint32_t);
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+       uint32_t HDMI_ACP_SEND;
+#endif
        SE_REG_FIELD_LIST_DCN2_0(uint32_t);
        SE_REG_FIELD_LIST_DCN3_0(uint32_t);
+       SE_REG_FIELD_LIST_DCN3_2(uint32_t);
+
 };
 
 struct dcn10_stream_encoder {