drm/amd/display: move panel power seq to new panel struct

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_resource.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 3b71898..7dd0945 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -51,6 +51,7 @@
 #include "dce112/dce112_resource.h"
 #include "dcn10_hubp.h"
 #include "dcn10_hubbub.h"
+#include "dce/dce_panel.h"
 
 #include "soc15_hw_ip.h"
 #include "vega10_ip_offset.h"
@@ -321,6 +322,18 @@ static const struct dcn10_link_enc_mask le_mask = {
                LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
 };
 
+static const struct dce_panel_registers panel_regs[] = {
+       { DCN_PANEL_REG_LIST() }
+};
+
+static const struct dce_panel_shift panel_shift = {
+       DCE_PANEL_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_panel_mask panel_mask = {
+       DCE_PANEL_MASK_SH_LIST(_MASK)
+};
+
 static const struct dce110_aux_registers_shift aux_shift = {
        DCN10_AUX_MASK_SH_LIST(__SHIFT)
 };
@@ -552,7 +565,8 @@ static const struct dc_plane_cap plane_cap = {
        .pixel_format_support = {
                        .argb8888 = true,
                        .nv12 = true,
-                       .fp16 = true
+                       .fp16 = true,
+                       .p010 = true
        },
 
        .max_upscale_factor = {
@@ -570,7 +584,7 @@ static const struct dc_plane_cap plane_cap = {
 
 static const struct dc_debug_options debug_defaults_drv = {
                .sanity_checks = true,
-               .disable_dmcu = true,
+               .disable_dmcu = false,
                .force_abm_enable = false,
                .timing_trace = false,
                .clock_trace = true,
@@ -584,7 +598,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                .disable_pplib_clock_request = false,
                .disable_pplib_wm_range = false,
                .pplib_wm_report_mode = WM_REPORT_DEFAULT,
-               .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+               .pipe_split_policy = MPC_SPLIT_DYNAMIC,
                .force_single_disp_pipe_split = true,
                .disable_dcc = DCC_ENABLE,
                .voltage_align_fclk = true,
@@ -598,7 +612,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
-               .disable_dmcu = true,
+               .disable_dmcu = false,
                .force_abm_enable = false,
                .timing_trace = true,
                .clock_trace = true,
@@ -806,6 +820,23 @@ struct link_encoder *dcn10_link_encoder_create(
        return &enc10->base;
 }
 
+static struct panel *dcn10_panel_create(const struct panel_init_data *init_data)
+{
+       struct dce_panel *panel =
+               kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
+
+       if (!panel)
+               return NULL;
+
+       dce_panel_construct(panel,
+                       init_data,
+                       &panel_regs[init_data->inst],
+                       &panel_shift,
+                       &panel_mask);
+
+       return &panel->base;
+}
+
 struct clock_source *dcn10_clock_source_create(
        struct dc_context *ctx,
        struct dc_bios *bios,
@@ -1233,7 +1264,7 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont
        return DC_OK;
 }
 
-static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)
+static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
 {
        enum dc_status result = DC_OK;
 
@@ -1290,12 +1321,13 @@ static const struct dc_cap_funcs cap_funcs = {
 static const struct resource_funcs dcn10_res_pool_funcs = {
        .destroy = dcn10_destroy_resource_pool,
        .link_enc_create = dcn10_link_encoder_create,
+       .panel_create = dcn10_panel_create,
        .validate_bandwidth = dcn_validate_bandwidth,
        .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
        .validate_plane = dcn10_validate_plane,
        .validate_global = dcn10_validate_global,
        .add_stream_to_ctx = dcn10_add_stream_to_ctx,
-       .get_default_swizzle_mode = dcn10_get_default_swizzle_mode,
+       .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
        .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
 };