drm/amd/display: Add primary tmz_c and meta tmz tmz_c.

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hubp.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 585b333..39b72f6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -73,6 +73,9 @@ static void hubp1_disconnect(struct hubp *hubp)
 
        REG_UPDATE(DCHUBP_CNTL,
                        HUBP_TTU_DISABLE, 1);
+
+       REG_UPDATE(CURSOR_CONTROL,
+                       CURSOR_ENABLE, 0);
 }
 
 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
@@ -296,8 +299,9 @@ bool hubp1_program_surface_flip_and_addr(
                if (address->grph.addr.quad_part == 0)
                        break;
 
-               REG_UPDATE(DCSURF_SURFACE_CONTROL,
-                               PRIMARY_SURFACE_TMZ, address->tmz_surface);
+               REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+                               PRIMARY_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
 
                if (address->grph.meta_addr.quad_part != 0) {
                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
@@ -322,8 +326,11 @@ bool hubp1_program_surface_flip_and_addr(
                        || address->video_progressive.chroma_addr.quad_part == 0)
                        break;
 
-               REG_UPDATE(DCSURF_SURFACE_CONTROL,
-                               PRIMARY_SURFACE_TMZ, address->tmz_surface);
+               REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                               PRIMARY_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 
                if (address->video_progressive.luma_meta_addr.quad_part != 0) {
                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
@@ -365,8 +372,11 @@ bool hubp1_program_surface_flip_and_addr(
                if (address->grph_stereo.right_addr.quad_part == 0)
                        break;
 
-               REG_UPDATE(DCSURF_SURFACE_CONTROL,
-                               PRIMARY_SURFACE_TMZ, address->tmz_surface);
+               REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                               PRIMARY_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 
                if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 
@@ -909,6 +919,21 @@ void hubp1_cursor_set_position(
        /* TODO Handle surface pixel formats other than 4:4:4 */
 }
 
+void hubp1_clk_cntl(struct hubp *hubp, bool enable)
+{
+       struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+       uint32_t clk_enable = enable ? 1 : 0;
+
+       REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
+}
+
+void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
+{
+       struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+       REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
+}
+
 static struct hubp_funcs dcn10_hubp_funcs = {
        .hubp_program_surface_flip_and_addr =
                        hubp1_program_surface_flip_and_addr,
@@ -925,6 +950,8 @@ static struct hubp_funcs dcn10_hubp_funcs = {
        .set_cursor_attributes  = hubp1_cursor_set_attributes,
        .set_cursor_position    = hubp1_cursor_set_position,
        .hubp_disconnect = hubp1_disconnect,
+       .hubp_clk_cntl = hubp1_clk_cntl,
+       .hubp_vtg_sel = hubp1_vtg_sel,
 };
 
 /*****************************************/