drm/amd/display: Power eDP panel back ON before link training retry

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_hwss.c

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index dd88eb3..81c0263 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -104,6 +104,12 @@ void dp_enable_link_phy(
        struct clock_source *dp_cs =
                        link->dc->res_pool->dp_clock_source;
        unsigned int i;
+
+       if (link->connector_signal == SIGNAL_TYPE_EDP) {
+               link->dc->hwss.edp_power_control(link, true);
+               link->dc->hwss.edp_wait_for_hpd_ready(link, true);
+       }
+
        /* If the current pixel clock source is not DTO(happens after
         * switching from HDMI passive dongle to DP on the same connector),
         * switch the pixel clock source to DTO.