}
}
+static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
+{
+ int i;
+ uint32_t count = 0;
+
+ for (i = 0; i < num_links; i++) {
+ if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
+ links[i]->is_internal_display)
+ count++;
+ }
+
+ return count;
+}
+
static bool create_links(
struct dc *dc,
uint32_t num_virtual_links)
virtual_link_encoder_construct(link->link_enc, &enc_init);
}
+ dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
+
return true;
failed_alloc:
* calculate the crc.
*/
bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
- bool enable, bool continuous)
+ struct crc_params *crc_window, bool enable, bool continuous)
{
int i;
struct pipe_ctx *pipe;
if (i == MAX_PIPES)
return false;
- /* Always capture the full frame */
+ /* By default, capture the full frame */
param.windowa_x_start = 0;
param.windowa_y_start = 0;
param.windowa_x_end = pipe->stream->timing.h_addressable;
param.windowb_x_end = pipe->stream->timing.h_addressable;
param.windowb_y_end = pipe->stream->timing.v_addressable;
+ if (crc_window) {
+ param.windowa_x_start = crc_window->windowa_x_start;
+ param.windowa_y_start = crc_window->windowa_y_start;
+ param.windowa_x_end = crc_window->windowa_x_end;
+ param.windowa_y_end = crc_window->windowa_y_end;
+ param.windowb_x_start = crc_window->windowb_x_start;
+ param.windowb_y_start = crc_window->windowb_y_start;
+ param.windowb_x_end = crc_window->windowb_x_end;
+ param.windowb_y_end = crc_window->windowb_y_end;
+ }
+
param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
param.odm_mode = pipe->next_odm_pipe ? 1:0;
dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
if (!dc->clk_mgr)
goto fail;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+#ifdef CONFIG_DRM_AMD_DC_DCN
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
#endif
if (stream == NULL)
continue;
+ // only looking for first odm pipe
+ if (pipe->prev_odm_pipe)
+ continue;
+
if (stream->link->local_sink &&
stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
link = stream->link;
}
- if (link != NULL) {
+ if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
unsigned int enc_inst, tg_inst = 0;
unsigned int pix_clk_100hz;
int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_allow_idle_optimizations(dc, false);
#endif
return (result == DC_OK);
}
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dc_acquire_release_mpc_3dlut(
struct dc *dc, bool acquire,
struct dc_stream_state *stream,
int i;
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dc->idle_optimizations_allowed)
overall_type = UPDATE_TYPE_FULL;
}
if (update_type == UPDATE_TYPE_FULL) {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_allow_idle_optimizations(dc, false);
#endif
return NULL;
}
+struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
+{
+ uint8_t i;
+ struct dc_context *ctx = link->ctx;
+
+ for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
+ if (ctx->dc->current_state->streams[i]->link == link)
+ return ctx->dc->current_state->streams[i];
+ }
+
+ return NULL;
+}
+
enum dc_irq_source dc_interrupt_to_irq_source(
struct dc *dc,
uint32_t src_id,
if (link->psr_settings.psr_feature_enabled) {
if (enable && !link->psr_settings.psr_allow_active)
- return dc_link_set_psr_allow_active(link, true, false);
+ return dc_link_set_psr_allow_active(link, true, false, false);
else if (!enable && link->psr_settings.psr_allow_active)
- return dc_link_set_psr_allow_active(link, false, true);
+ return dc_link_set_psr_allow_active(link, false, true, false);
}
}
return true;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
void dc_allow_idle_optimizations(struct dc *dc, bool allow)
{