Merge branch 'address-masking'
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / vce_v4_0.c
index 57b85bb..0748bf4 100644 (file)
@@ -466,7 +466,7 @@ static int vce_v4_0_sw_init(void *handle)
                enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i);
 
                ring = &adev->vce.ring[i];
-               ring->vm_hub = AMDGPU_MMHUB_0;
+               ring->vm_hub = AMDGPU_MMHUB0(0);
                sprintf(ring->name, "vce%d", i);
                if (amdgpu_sriov_vf(adev)) {
                        /* DOORBELL only works under SRIOV */
@@ -486,11 +486,6 @@ static int vce_v4_0_sw_init(void *handle)
                        return r;
        }
 
-
-       r = amdgpu_vce_entity_init(adev);
-       if (r)
-               return r;
-
        r = amdgpu_virt_alloc_mm_table(adev);
        if (r)
                return r;
@@ -1107,7 +1102,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
        .get_rptr = vce_v4_0_ring_get_rptr,
        .get_wptr = vce_v4_0_ring_get_wptr,
        .set_wptr = vce_v4_0_ring_set_wptr,
-       .parse_cs = amdgpu_vce_ring_parse_cs_vm,
+       .patch_cs_in_place = amdgpu_vce_ring_parse_cs_vm,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +