Linux 6.9-rc1

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / soc15.c

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c64c01e..dec81cc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -574,11 +574,34 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
                return AMD_RESET_METHOD_MODE1;
 }
 
+static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
+{
+       u32 sol_reg;
+
+       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+
+       /* Will reset for the following suspend abort cases.
+        * 1) Only reset limit on APU side, dGPU hasn't checked yet.
+        * 2) S3 suspend abort and TOS already launched.
+        */
+       if (adev->flags & AMD_IS_APU && adev->in_s3 &&
+                       !adev->suspend_complete &&
+                       sol_reg)
+               return true;
+
+       return false;
+}
+
 static int soc15_asic_reset(struct amdgpu_device *adev)
 {
        /* original raven doesn't have full asic reset */
-       if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
-           (adev->apu_flags & AMD_APU_IS_RAVEN2))
+       /* On the latest Raven, the GPU reset can be performed
+        * successfully. So now, temporarily enable it for the
+        * S3 suspend abort case.
+        */
+       if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
+           (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
+               !soc15_need_reset_on_resume(adev))
                return 0;
 
        switch (soc15_asic_reset_method(adev)) {
@@ -895,7 +918,6 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
        .get_config_memsize = &soc15_get_config_memsize,
        .need_full_reset = &soc15_need_full_reset,
        .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
-       .get_pcie_usage = &amdgpu_nbio_get_pcie_usage,
        .need_reset_on_init = &soc15_need_reset_on_init,
        .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
        .supports_baco = &soc15_supports_baco,
@@ -1278,7 +1300,8 @@ static int soc15_common_hw_fini(void *handle)
        if (amdgpu_sriov_vf(adev))
                xgpu_ai_mailbox_put_irq(adev);
 
-       if (adev->nbio.ras_if &&
+       if ((!amdgpu_sriov_vf(adev)) &&
+           adev->nbio.ras_if &&
            amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
                if (adev->nbio.ras &&
                    adev->nbio.ras->init_ras_controller_interrupt)
@@ -1298,24 +1321,6 @@ static int soc15_common_suspend(void *handle)
        return soc15_common_hw_fini(adev);
 }
 
-static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
-{
-       u32 sol_reg;
-
-       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-
-       /* Will reset for the following suspend abort cases.
-        * 1) Only reset limit on APU side, dGPU hasn't checked yet.
-        * 2) S3 suspend abort and TOS already launched.
-        */
-       if (adev->flags & AMD_IS_APU && adev->in_s3 &&
-                       !adev->suspend_complete &&
-                       sol_reg)
-               return true;
-
-       return false;
-}
-
 static int soc15_common_resume(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;